Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
484 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
487 resets = <&gcc ADM0_RESET>,
488 <&gcc ADM0_PBUS_RESET>,
489 <&gcc ADM0_C0_RESET>,
490 <&gcc ADM0_C1_RESET>,
491 <&gcc ADM0_C2_RESET>;
514 clocks = <&gcc GSBI2_H_CLK>;
528 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
538 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
551 clocks = <&gcc GSBI4_H_CLK>;
565 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
575 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
588 clocks = <&gcc GSBI5_H_CLK>;
602 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
612 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
625 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
639 clocks = <&gcc GSBI7_H_CLK>;
651 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
660 clocks = <&gcc PRNG_CLK>;
668 clocks = <&gcc SATA_PHY_CFG_CLK>;
682 clocks = <&gcc EBI2_CLK>,
683 <&gcc EBI2_AON_CLK>;
703 clocks = <&gcc SFAB_SATA_S_H_CLK>,
704 <&gcc SATA_H_CLK>,
705 <&gcc SATA_A_CLK>,
706 <&gcc SATA_RXOOB_CLK>,
707 <&gcc SATA_PMALIVE_CLK>;
711 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
738 gcc: clock-controller@900000 { label
739 compatible = "qcom,gcc-ipq8064";
768 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
783 compatible = "qcom,kpss-gcc", "syscon";
785 clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
823 clocks = <&gcc PCIE_A_CLK>,
824 <&gcc PCIE_H_CLK>,
825 <&gcc PCIE_PHY_CLK>,
826 <&gcc PCIE_AUX_CLK>,
827 <&gcc PCIE_ALT_REF_CLK>;
830 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
833 resets = <&gcc PCIE_ACLK_RESET>,
834 <&gcc PCIE_HCLK_RESET>,
835 <&gcc PCIE_POR_RESET>,
836 <&gcc PCIE_PCI_RESET>,
837 <&gcc PCIE_PHY_RESET>,
838 <&gcc PCIE_EXT_RESET>;
874 clocks = <&gcc PCIE_1_A_CLK>,
875 <&gcc PCIE_1_H_CLK>,
876 <&gcc PCIE_1_PHY_CLK>,
877 <&gcc PCIE_1_AUX_CLK>,
878 <&gcc PCIE_1_ALT_REF_CLK>;
881 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
884 resets = <&gcc PCIE_1_ACLK_RESET>,
885 <&gcc PCIE_1_HCLK_RESET>,
886 <&gcc PCIE_1_POR_RESET>,
887 <&gcc PCIE_1_PCI_RESET>,
888 <&gcc PCIE_1_PHY_RESET>,
889 <&gcc PCIE_1_EXT_RESET>;
925 clocks = <&gcc PCIE_2_A_CLK>,
926 <&gcc PCIE_2_H_CLK>,
927 <&gcc PCIE_2_PHY_CLK>,
928 <&gcc PCIE_2_AUX_CLK>,
929 <&gcc PCIE_2_ALT_REF_CLK>;
932 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
935 resets = <&gcc PCIE_2_ACLK_RESET>,
936 <&gcc PCIE_2_HCLK_RESET>,
937 <&gcc PCIE_2_POR_RESET>,
938 <&gcc PCIE_2_PCI_RESET>,
939 <&gcc PCIE_2_PHY_RESET>,
940 <&gcc PCIE_2_EXT_RESET>;
980 clocks = <&gcc GMAC_CORE1_CLK>;
983 resets = <&gcc GMAC_CORE1_RESET>,
984 <&gcc GMAC_AHB_RESET>;
1004 clocks = <&gcc GMAC_CORE2_CLK>;
1007 resets = <&gcc GMAC_CORE2_RESET>,
1008 <&gcc GMAC_AHB_RESET>;
1028 clocks = <&gcc GMAC_CORE3_CLK>;
1031 resets = <&gcc GMAC_CORE3_RESET>,
1032 <&gcc GMAC_AHB_RESET>;
1052 clocks = <&gcc GMAC_CORE4_CLK>;
1055 resets = <&gcc GMAC_CORE4_RESET>,
1056 <&gcc GMAC_AHB_RESET>;
1065 clocks = <&gcc USB30_0_UTMI_CLK>;
1075 clocks = <&gcc USB30_0_MASTER_CLK>;
1087 clocks = <&gcc USB30_0_MASTER_CLK>;
1092 resets = <&gcc USB30_0_MASTER_RESET>;
1111 clocks = <&gcc USB30_1_UTMI_CLK>;
1119 clocks = <&gcc USB30_1_MASTER_CLK>;
1129 clocks = <&gcc USB30_1_MASTER_CLK>;
1134 resets = <&gcc USB30_1_MASTER_RESET>;
1162 clocks = <&gcc SDC1_H_CLK>;
1172 clocks = <&gcc SDC3_H_CLK>;
1191 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1211 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;