Lines Matching +full:0 +full:xcd00
23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
53 polling-delay-passive = <0>;
54 polling-delay = <0>;
55 thermal-sensors = <&tsens 0>;
73 polling-delay-passive = <0>;
74 polling-delay = <0>;
93 polling-delay-passive = <0>;
94 polling-delay = <0>;
113 polling-delay-passive = <0>;
114 polling-delay = <0>;
133 polling-delay-passive = <0>;
134 polling-delay = <0>;
153 polling-delay-passive = <0>;
154 polling-delay = <0>;
173 polling-delay-passive = <0>;
174 polling-delay = <0>;
193 polling-delay-passive = <0>;
194 polling-delay = <0>;
213 polling-delay-passive = <0>;
214 polling-delay = <0>;
233 polling-delay-passive = <0>;
234 polling-delay = <0>;
253 polling-delay-passive = <0>;
254 polling-delay = <0>;
275 reg = <0x0 0x0>;
290 reg = <0x40000000 0x1000000>;
295 reg = <0x41000000 0x200000>;
303 #clock-cells = <0>;
309 #clock-cells = <0>;
316 #clock-cells = <0>;
343 reg = <0x28100000 0x10000>;
349 reg = <0x800000 0x4000>;
352 gpio-ranges = <&qcom_pinmux 0 0 69>;
443 reg = <0x02000000 0x1000>,
444 <0x02002000 0x1000>;
460 reg = <0x0200a000 0x100>;
465 cpu-offset = <0x80000>;
470 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
475 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
480 reg = <0x18300000 0x100000>;
493 qcom,ee = <0>;
500 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
506 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
513 reg = <0x12480000 0x100>;
525 reg = <0x12490000 0x1000>,
526 <0x12480000 0x1000>;
535 reg = <0x124a0000 0x1000>;
543 #size-cells = <0>;
550 reg = <0x16300000 0x100>;
562 reg = <0x16340000 0x1000>,
563 <0x16300000 0x1000>;
572 reg = <0x16380000 0x1000>;
580 #size-cells = <0>;
587 reg = <0x1a200000 0x100>;
599 reg = <0x1a240000 0x1000>,
600 <0x1a200000 0x1000>;
609 reg = <0x1a280000 0x1000>;
617 #size-cells = <0>;
622 reg = <0x1a280000 0x1000>;
630 #size-cells = <0>;
638 reg = <0x16600000 0x100>;
648 reg = <0x16640000 0x1000>,
649 <0x16600000 0x1000>;
659 reg = <0x1a500000 0x200>;
666 reg = <0x1b400000 0x200>;
671 #phy-cells = <0>;
677 reg = <0x1ac00000 0x800>;
679 pinctrl-0 = <&nand_pins>;
692 #size-cells = <0>;
699 reg = <0x29000000 0x180>;
721 reg = <0x00500000 0x1000>;
727 reg = <0x00700000 0x1000>;
731 reg = <0x400 0xb>;
734 reg = <0x410 0xb>;
740 reg = <0x00900000 0x4000>;
760 reg = <0x108000 0x1000>;
761 qcom,ipc = <&l2cc 0x8 2>;
779 reg = <0x1a400000 0x100>;
784 reg = <0x2011000 0x1000>;
792 reg = <0x28000000 0x1000>;
799 reg = <0x1b500000 0x1000
800 0x1b502000 0x80
801 0x1b600000 0x100
802 0x0ff00000 0x100000>;
805 linux,pci-domain = <0>;
806 bus-range = <0x00 0xff>;
811 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
812 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
817 interrupt-map-mask = <0 0 0 0x7>;
818 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
819 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
820 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
821 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
841 pinctrl-0 = <&pcie0_pins>;
850 reg = <0x1b700000 0x1000
851 0x1b702000 0x80
852 0x1b800000 0x100
853 0x31f00000 0x100000>;
857 bus-range = <0x00 0xff>;
862 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
863 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
868 interrupt-map-mask = <0 0 0 0x7>;
869 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
870 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
871 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
872 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
892 pinctrl-0 = <&pcie1_pins>;
901 reg = <0x1b900000 0x1000
902 0x1b902000 0x80
903 0x1ba00000 0x100
904 0x35f00000 0x100000>;
908 bus-range = <0x00 0xff>;
913 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
914 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
919 interrupt-map-mask = <0 0 0 0x7>;
920 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
921 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
922 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
923 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
943 pinctrl-0 = <&pcie2_pins>;
952 reg = <0x03000000 0x0000FFFF>;
957 reg = <0x1bb00000 0x000001FF>;
963 snps,blen = <16 0 0 0 0 0 0>;
969 reg = <0x37000000 0x200000>;
993 reg = <0x37200000 0x200000>;
1017 reg = <0x37400000 0x200000>;
1041 reg = <0x37600000 0x200000>;
1064 reg = <0x100f8800 0x30>;
1067 #phy-cells = <0>;
1074 reg = <0x100f8830 0x30>;
1077 #phy-cells = <0>;
1086 reg = <0x100f8800 0x8000>;
1099 reg = <0x10000000 0xcd00>;
1110 reg = <0x110f8800 0x30>;
1113 #phy-cells = <0>;
1118 reg = <0x110f8830 0x30>;
1121 #phy-cells = <0>;
1128 reg = <0x110f8800 0x8000>;
1141 reg = <0x11000000 0xcd00>;
1160 reg = <0x12402000 0x8000>;
1165 qcom,ee = <0>;
1170 reg = <0x12182000 0x8000>;
1175 qcom,ee = <0>;
1187 arm,primecell-periphid = <0x00051180>;
1188 reg = <0x12400000 0x2000>;
1206 arm,primecell-periphid = <0x00051180>;
1208 reg = <0x12180000 0x2000>;