Lines Matching +full:flow +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0+
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
55 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
60 * the Line Control Register is set to 0xBFh. in cls_set_cts_flow_control()
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
66 /* Turn on CTS flow control, turn off IXON flow control */ in cls_set_cts_flow_control()
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
73 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_cts_flow_control()
76 * Enable interrupts for CTS flow, turn off interrupts for in cls_set_cts_flow_control()
81 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_cts_flow_control()
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
88 &ch->ch_cls_uart->isr_fcr); in cls_set_cts_flow_control()
90 ch->ch_t_tlevel = 16; in cls_set_cts_flow_control()
95 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
96 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
101 * the Line Control Register is set to 0xBFh. in cls_set_ixon_flow_control()
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
107 /* Turn on IXON flow control, turn off CTS flow control */ in cls_set_ixon_flow_control()
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control()
115 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixon_flow_control()
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixon_flow_control()
117 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixon_flow_control()
120 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixon_flow_control()
123 * Disable interrupts for CTS flow, turn on interrupts for in cls_set_ixon_flow_control()
128 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixon_flow_control()
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
135 &ch->ch_cls_uart->isr_fcr); in cls_set_ixon_flow_control()
140 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
141 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
146 * the Line Control Register is set to 0xBFh. in cls_set_no_output_flow_control()
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
152 /* Turn off IXON flow control, turn off CTS flow control */ in cls_set_no_output_flow_control()
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
159 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_output_flow_control()
162 * Disable interrupts for CTS flow, turn off interrupts for in cls_set_no_output_flow_control()
167 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_output_flow_control()
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
174 &ch->ch_cls_uart->isr_fcr); in cls_set_no_output_flow_control()
176 ch->ch_r_watermark = 0; in cls_set_no_output_flow_control()
177 ch->ch_t_tlevel = 16; in cls_set_no_output_flow_control()
178 ch->ch_r_tlevel = 16; in cls_set_no_output_flow_control()
183 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
184 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
189 * the Line Control Register is set to 0xBFh. in cls_set_rts_flow_control()
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
195 /* Turn on RTS flow control, turn off IXOFF flow control */ in cls_set_rts_flow_control()
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
202 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_rts_flow_control()
204 /* Enable interrupts for RTS flow */ in cls_set_rts_flow_control()
206 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_rts_flow_control()
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
213 &ch->ch_cls_uart->isr_fcr); in cls_set_rts_flow_control()
215 ch->ch_r_watermark = 4; in cls_set_rts_flow_control()
216 ch->ch_r_tlevel = 8; in cls_set_rts_flow_control()
221 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
222 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
227 * the Line Control Register is set to 0xBFh. in cls_set_ixoff_flow_control()
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
233 /* Turn on IXOFF flow control, turn off RTS flow control */ in cls_set_ixoff_flow_control()
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control()
241 writeb(0, &ch->ch_cls_uart->lsr); in cls_set_ixoff_flow_control()
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); in cls_set_ixoff_flow_control()
243 writeb(0, &ch->ch_cls_uart->spr); in cls_set_ixoff_flow_control()
246 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_ixoff_flow_control()
248 /* Disable interrupts for RTS flow */ in cls_set_ixoff_flow_control()
250 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_ixoff_flow_control()
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
257 &ch->ch_cls_uart->isr_fcr); in cls_set_ixoff_flow_control()
262 u8 lcrb = readb(&ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
263 u8 ier = readb(&ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
268 * the Line Control Register is set to 0xBFh. in cls_set_no_input_flow_control()
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
274 /* Turn off IXOFF flow control, turn off RTS flow control */ in cls_set_no_input_flow_control()
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
281 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_set_no_input_flow_control()
283 /* Disable interrupts for RTS flow */ in cls_set_no_input_flow_control()
285 writeb(ier, &ch->ch_cls_uart->ier); in cls_set_no_input_flow_control()
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
292 &ch->ch_cls_uart->isr_fcr); in cls_set_no_input_flow_control()
294 ch->ch_t_tlevel = 16; in cls_set_no_input_flow_control()
295 ch->ch_r_tlevel = 16; in cls_set_no_input_flow_control()
309 spin_lock_irqsave(&ch->ch_lock, lock_flags); in cls_clear_break()
312 if (ch->ch_flags & CH_BREAK_SENDING) { in cls_clear_break()
313 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_clear_break()
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_clear_break()
317 ch->ch_flags &= ~(CH_BREAK_SENDING); in cls_clear_break()
318 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in cls_clear_break()
322 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in cls_clear_break()
327 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_disable_receiver()
330 writeb(tmp, &ch->ch_cls_uart->ier); in cls_disable_receiver()
335 u8 tmp = readb(&ch->ch_cls_uart->ier); in cls_enable_receiver()
338 writeb(tmp, &ch->ch_cls_uart->ier); in cls_enable_receiver()
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
362 spin_lock_irqsave(&ch->ch_lock, flags); in cls_copy_data_from_uart_to_queue()
365 head = ch->ch_r_head & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
366 tail = ch->ch_r_tail & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
369 linestatus = ch->ch_cached_lsr; in cls_copy_data_from_uart_to_queue()
370 ch->ch_cached_lsr = 0; in cls_copy_data_from_uart_to_queue()
373 qleft = tail - head - 1; in cls_copy_data_from_uart_to_queue()
381 if (ch->ch_c_iflag & IGNBRK) in cls_copy_data_from_uart_to_queue()
389 linestatus = readb(&ch->ch_cls_uart->lsr); in cls_copy_data_from_uart_to_queue()
403 discard = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
417 ch->ch_r_tail = tail; in cls_copy_data_from_uart_to_queue()
418 ch->ch_err_overrun++; in cls_copy_data_from_uart_to_queue()
422 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE in cls_copy_data_from_uart_to_queue()
424 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); in cls_copy_data_from_uart_to_queue()
426 qleft--; in cls_copy_data_from_uart_to_queue()
428 if (ch->ch_equeue[head] & UART_LSR_PE) in cls_copy_data_from_uart_to_queue()
429 ch->ch_err_parity++; in cls_copy_data_from_uart_to_queue()
430 if (ch->ch_equeue[head] & UART_LSR_BI) in cls_copy_data_from_uart_to_queue()
431 ch->ch_err_break++; in cls_copy_data_from_uart_to_queue()
432 if (ch->ch_equeue[head] & UART_LSR_FE) in cls_copy_data_from_uart_to_queue()
433 ch->ch_err_frame++; in cls_copy_data_from_uart_to_queue()
437 ch->ch_rxcount++; in cls_copy_data_from_uart_to_queue()
443 ch->ch_r_head = head & RQUEUEMASK; in cls_copy_data_from_uart_to_queue()
444 ch->ch_e_head = head & EQUEUEMASK; in cls_copy_data_from_uart_to_queue()
446 spin_unlock_irqrestore(&ch->ch_lock, flags); in cls_copy_data_from_uart_to_queue()
460 circ = &ch->uart_port.state->xmit; in cls_copy_data_from_queue_to_uart()
467 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) in cls_copy_data_from_queue_to_uart()
471 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) in cls_copy_data_from_queue_to_uart()
477 tail = circ->tail & (UART_XMIT_SIZE - 1); in cls_copy_data_from_queue_to_uart()
484 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); in cls_copy_data_from_queue_to_uart()
485 tail = (tail + 1) & (UART_XMIT_SIZE - 1); in cls_copy_data_from_queue_to_uart()
486 n--; in cls_copy_data_from_queue_to_uart()
487 ch->ch_txcount++; in cls_copy_data_from_queue_to_uart()
492 circ->tail = tail & (UART_XMIT_SIZE - 1); in cls_copy_data_from_queue_to_uart()
494 if (len_written > ch->ch_t_tlevel) in cls_copy_data_from_queue_to_uart()
495 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_copy_data_from_queue_to_uart()
498 uart_write_wakeup(&ch->uart_port); in cls_copy_data_from_queue_to_uart()
505 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in cls_parse_modem()
507 ch->ch_portnum, msignals); in cls_parse_modem()
517 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); in cls_parse_modem()
519 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS); in cls_parse_modem()
522 ch->ch_mistat |= UART_MSR_DCD; in cls_parse_modem()
524 ch->ch_mistat &= ~UART_MSR_DCD; in cls_parse_modem()
527 ch->ch_mistat |= UART_MSR_DSR; in cls_parse_modem()
529 ch->ch_mistat &= ~UART_MSR_DSR; in cls_parse_modem()
532 ch->ch_mistat |= UART_MSR_RI; in cls_parse_modem()
534 ch->ch_mistat &= ~UART_MSR_RI; in cls_parse_modem()
537 ch->ch_mistat |= UART_MSR_CTS; in cls_parse_modem()
539 ch->ch_mistat &= ~UART_MSR_CTS; in cls_parse_modem()
541 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in cls_parse_modem()
543 ch->ch_portnum, in cls_parse_modem()
544 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), in cls_parse_modem()
545 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), in cls_parse_modem()
546 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), in cls_parse_modem()
547 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), in cls_parse_modem()
548 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), in cls_parse_modem()
549 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); in cls_parse_modem()
564 if (port >= brd->nasync) in cls_parse_isr()
567 ch = brd->channels[port]; in cls_parse_isr()
573 isr = readb(&ch->ch_cls_uart->isr_fcr); in cls_parse_isr()
581 /* Read data from uart -> queue */ in cls_parse_isr()
588 /* Transfer data (if any) from Write Queue -> UART. */ in cls_parse_isr()
589 spin_lock_irqsave(&ch->ch_lock, flags); in cls_parse_isr()
590 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_parse_isr()
591 spin_unlock_irqrestore(&ch->ch_lock, flags); in cls_parse_isr()
602 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_parse_isr()
616 &ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
620 tmp = readb(&ch->ch_cls_uart->isr_fcr); in cls_flush_uart_write()
622 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in cls_flush_uart_write()
629 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_flush_uart_write()
657 if (ch->ch_startc != __DISABLED_CHAR) { in cls_send_start_character()
658 ch->ch_xon_sends++; in cls_send_start_character()
659 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); in cls_send_start_character()
668 if (ch->ch_stopc != __DISABLED_CHAR) { in cls_send_stop_character()
669 ch->ch_xoff_sends++; in cls_send_stop_character()
670 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); in cls_send_stop_character()
689 bd = ch->ch_bd; in cls_param()
696 if ((ch->ch_c_cflag & (CBAUD)) == 0) { in cls_param()
697 ch->ch_r_head = 0; in cls_param()
698 ch->ch_r_tail = 0; in cls_param()
699 ch->ch_e_head = 0; in cls_param()
700 ch->ch_e_tail = 0; in cls_param()
706 ch->ch_flags |= (CH_BAUD0); in cls_param()
707 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); in cls_param()
712 cflag = C_BAUD(ch->uart_port.state->port.tty); in cls_param()
721 if (ch->ch_flags & CH_BAUD0) in cls_param()
722 ch->ch_flags &= ~(CH_BAUD0); in cls_param()
724 if (ch->ch_c_cflag & PARENB) in cls_param()
727 if (!(ch->ch_c_cflag & PARODD)) in cls_param()
735 if (ch->ch_c_cflag & CMSPAR) in cls_param()
739 if (ch->ch_c_cflag & CSTOPB) in cls_param()
742 switch (ch->ch_c_cflag & CSIZE) { in cls_param()
758 ier = readb(&ch->ch_cls_uart->ier); in cls_param()
759 uart_lcr = readb(&ch->ch_cls_uart->lcr); in cls_param()
761 quot = ch->ch_bd->bd_dividend / baud; in cls_param()
764 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); in cls_param()
765 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); in cls_param()
766 writeb((quot >> 8), &ch->ch_cls_uart->ier); in cls_param()
767 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
771 writeb(lcr, &ch->ch_cls_uart->lcr); in cls_param()
773 if (ch->ch_c_cflag & CREAD) in cls_param()
778 writeb(ier, &ch->ch_cls_uart->ier); in cls_param()
780 if (ch->ch_c_cflag & CRTSCTS) in cls_param()
782 else if (ch->ch_c_iflag & IXON) { in cls_param()
785 * then we should disable flow control. in cls_param()
787 if ((ch->ch_startc == __DISABLED_CHAR) || in cls_param()
788 (ch->ch_stopc == __DISABLED_CHAR)) in cls_param()
795 if (ch->ch_c_cflag & CRTSCTS) in cls_param()
797 else if (ch->ch_c_iflag & IXOFF) { in cls_param()
800 * then we should disable flow control. in cls_param()
802 if ((ch->ch_startc == __DISABLED_CHAR) || in cls_param()
803 (ch->ch_stopc == __DISABLED_CHAR)) in cls_param()
813 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); in cls_param()
829 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); in cls_intr()
835 uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET); in cls_intr()
837 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", in cls_intr()
841 jsm_dbg(INTR, &brd->pci_dev, in cls_intr()
843 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in cls_intr()
850 for (i = 0; i < brd->nasync; i++) in cls_intr()
853 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in cls_intr()
861 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); in cls_uart_init()
864 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_init()
868 * the Line Control Register is set to 0xBFh. in cls_uart_init()
870 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); in cls_uart_init()
872 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); in cls_uart_init()
877 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
880 writeb(lcrb, &ch->ch_cls_uart->lcr); in cls_uart_init()
883 readb(&ch->ch_cls_uart->txrx); in cls_uart_init()
886 &ch->ch_cls_uart->isr_fcr); in cls_uart_init()
889 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_uart_init()
891 readb(&ch->ch_cls_uart->lsr); in cls_uart_init()
892 readb(&ch->ch_cls_uart->msr); in cls_uart_init()
901 writeb(0, &ch->ch_cls_uart->ier); in cls_uart_off()
913 u8 lsr = readb(&ch->ch_cls_uart->lsr); in cls_get_uart_bytes_left()
919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in cls_get_uart_bytes_left()
935 if (!(ch->ch_flags & CH_BREAK_SENDING)) { in cls_send_break()
936 u8 temp = readb(&ch->ch_cls_uart->lcr); in cls_send_break()
938 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); in cls_send_break()
939 ch->ch_flags |= (CH_BREAK_SENDING); in cls_send_break()
952 writeb(c, &ch->ch_cls_uart->txrx); in cls_send_immediate_char()