Lines Matching +full:0 +full:x34
63 return 0; in edp_pipe_is_enabled()
66 return 0; in edp_pipe_is_enabled()
84 return 0; in pipe_is_enabled()
91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
95 0x01, 0x04,
97 0xa5, 0x34, 0x20, 0x78, 0x23,
99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
101 0x21, 0x08, 0x00,
103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
118 0x00,
120 0xef,
125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
129 0x01, 0x04,
131 0xa5, 0x34, 0x20, 0x78, 0x23,
133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
135 0x21, 0x08, 0x00,
142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
157 0x00,
159 0x45,
163 #define DPCD_HEADER_SIZE 0xb
167 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
235 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
236 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
237 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
238 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
388 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
394 return 0; in setup_virtual_dp_monitor()
415 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { in intel_gvt_check_vblank_emulation()