Lines Matching +full:stm32 +full:- +full:cec
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32mp1-clks.h>
160 "ck_hse", "pll4_r", "clk-hse-div2"
372 /* STM32 Composite clock */
385 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
388 cfg->name, in _clk_hw_register_gate()
389 cfg->parent_name, in _clk_hw_register_gate()
390 cfg->flags, in _clk_hw_register_gate()
391 gate_cfg->reg_off + base, in _clk_hw_register_gate()
392 gate_cfg->bit_idx, in _clk_hw_register_gate()
393 gate_cfg->gate_flags, in _clk_hw_register_gate()
403 struct fixed_factor_cfg *ff_cfg = cfg->cfg; in _clk_hw_register_fixed_factor()
405 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, in _clk_hw_register_fixed_factor()
406 cfg->flags, ff_cfg->mult, in _clk_hw_register_fixed_factor()
407 ff_cfg->div); in _clk_hw_register_fixed_factor()
416 struct div_cfg *div_cfg = cfg->cfg; in _clk_hw_register_divider_table()
419 cfg->name, in _clk_hw_register_divider_table()
420 cfg->parent_name, in _clk_hw_register_divider_table()
421 cfg->flags, in _clk_hw_register_divider_table()
422 div_cfg->reg_off + base, in _clk_hw_register_divider_table()
423 div_cfg->shift, in _clk_hw_register_divider_table()
424 div_cfg->width, in _clk_hw_register_divider_table()
425 div_cfg->div_flags, in _clk_hw_register_divider_table()
426 div_cfg->table, in _clk_hw_register_divider_table()
436 struct mux_cfg *mux_cfg = cfg->cfg; in _clk_hw_register_mux()
438 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, in _clk_hw_register_mux()
439 cfg->num_parents, cfg->flags, in _clk_hw_register_mux()
440 mux_cfg->reg_off + base, mux_cfg->shift, in _clk_hw_register_mux()
441 mux_cfg->width, mux_cfg->mux_flags, lock); in _clk_hw_register_mux()
460 spin_lock_irqsave(gate->lock, flags); in mp1_gate_clk_disable()
461 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR); in mp1_gate_clk_disable()
462 spin_unlock_irqrestore(gate->lock, flags); in mp1_gate_clk_disable()
480 if (cfg->mmux) { in _get_stm32_mux()
483 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
485 mmux->mux.reg = cfg->mux->reg_off + base; in _get_stm32_mux()
486 mmux->mux.shift = cfg->mux->shift; in _get_stm32_mux()
487 mmux->mux.mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
488 mmux->mux.flags = cfg->mux->mux_flags; in _get_stm32_mux()
489 mmux->mux.table = cfg->mux->table; in _get_stm32_mux()
490 mmux->mux.lock = lock; in _get_stm32_mux()
491 mmux->mmux = cfg->mmux; in _get_stm32_mux()
492 mux_hw = &mmux->mux.hw; in _get_stm32_mux()
493 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw; in _get_stm32_mux()
498 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
500 mux->reg = cfg->mux->reg_off + base; in _get_stm32_mux()
501 mux->shift = cfg->mux->shift; in _get_stm32_mux()
502 mux->mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
503 mux->flags = cfg->mux->mux_flags; in _get_stm32_mux()
504 mux->table = cfg->mux->table; in _get_stm32_mux()
505 mux->lock = lock; in _get_stm32_mux()
506 mux_hw = &mux->hw; in _get_stm32_mux()
521 return ERR_PTR(-ENOMEM); in _get_stm32_div()
523 div->reg = cfg->div->reg_off + base; in _get_stm32_div()
524 div->shift = cfg->div->shift; in _get_stm32_div()
525 div->width = cfg->div->width; in _get_stm32_div()
526 div->flags = cfg->div->div_flags; in _get_stm32_div()
527 div->table = cfg->div->table; in _get_stm32_div()
528 div->lock = lock; in _get_stm32_div()
530 return &div->hw; in _get_stm32_div()
541 if (cfg->mgate) { in _get_stm32_gate()
544 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
546 mgate->gate.reg = cfg->gate->reg_off + base; in _get_stm32_gate()
547 mgate->gate.bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
548 mgate->gate.flags = cfg->gate->gate_flags; in _get_stm32_gate()
549 mgate->gate.lock = lock; in _get_stm32_gate()
550 mgate->mask = BIT(cfg->mgate->nbr_clk++); in _get_stm32_gate()
552 mgate->mgate = cfg->mgate; in _get_stm32_gate()
554 gate_hw = &mgate->gate.hw; in _get_stm32_gate()
559 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
561 gate->reg = cfg->gate->reg_off + base; in _get_stm32_gate()
562 gate->bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
563 gate->flags = cfg->gate->gate_flags; in _get_stm32_gate()
564 gate->lock = lock; in _get_stm32_gate()
566 gate_hw = &gate->hw; in _get_stm32_gate()
592 if (cfg->ops) in clk_stm32_register_gate_ops()
593 init.ops = cfg->ops; in clk_stm32_register_gate_ops()
597 return ERR_PTR(-ENOMEM); in clk_stm32_register_gate_ops()
599 hw->init = &init; in clk_stm32_register_gate_ops()
625 if (cfg->mux) { in clk_stm32_register_composite()
626 mux_hw = _get_stm32_mux(base, cfg->mux, lock); in clk_stm32_register_composite()
631 if (cfg->mux->ops) in clk_stm32_register_composite()
632 mux_ops = cfg->mux->ops; in clk_stm32_register_composite()
636 if (cfg->div) { in clk_stm32_register_composite()
637 div_hw = _get_stm32_div(base, cfg->div, lock); in clk_stm32_register_composite()
642 if (cfg->div->ops) in clk_stm32_register_composite()
643 div_ops = cfg->div->ops; in clk_stm32_register_composite()
647 if (cfg->gate) { in clk_stm32_register_composite()
648 gate_hw = _get_stm32_gate(base, cfg->gate, lock); in clk_stm32_register_composite()
653 if (cfg->gate->ops) in clk_stm32_register_composite()
654 gate_ops = cfg->gate->ops; in clk_stm32_register_composite()
670 clk_mgate->mgate->flag |= clk_mgate->mask; in mp1_mgate_clk_enable()
682 clk_mgate->mgate->flag &= ~clk_mgate->mask; in mp1_mgate_clk_disable()
684 if (clk_mgate->mgate->flag == 0) in mp1_mgate_clk_disable()
715 for (n = 0; n < clk_mmux->mmux->nbr_clk; n++) in clk_mmux_set_parent()
716 if (clk_mmux->mmux->hws[n] != hw) in clk_mmux_set_parent()
717 clk_hw_reparent(clk_mmux->mmux->hws[n], hwp); in clk_mmux_set_parent()
728 /* STM32 PLL */
753 return readl_relaxed(clk_elem->reg) & PLL_ON; in __pll_is_enabled()
766 spin_lock_irqsave(clk_elem->lock, flags); in pll_enable()
771 reg = readl_relaxed(clk_elem->reg); in pll_enable()
773 writel_relaxed(reg, clk_elem->reg); in pll_enable()
781 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY); in pll_enable()
786 } while (bit_status && --timeout); in pll_enable()
789 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_enable()
800 spin_lock_irqsave(clk_elem->lock, flags); in pll_disable()
802 reg = readl_relaxed(clk_elem->reg); in pll_disable()
804 writel_relaxed(reg, clk_elem->reg); in pll_disable()
806 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_disable()
814 reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET); in pll_frac_val()
829 reg = readl_relaxed(clk_elem->reg + 4); in pll_recalc_rate()
852 spin_lock_irqsave(clk_elem->lock, flags); in pll_is_enabled()
854 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_is_enabled()
879 return ERR_PTR(-ENOMEM); in clk_register_pll()
887 element->hw.init = &init; in clk_register_pll()
888 element->reg = reg; in clk_register_pll()
889 element->lock = lock; in clk_register_pll()
891 hw = &element->hw; in clk_register_pll()
923 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in __bestmult()
951 spin_lock_irqsave(tim_ker->lock, flags); in timer_ker_set_rate()
957 writel_relaxed(0, tim_ker->timpre); in timer_ker_set_rate()
960 writel_relaxed(1, tim_ker->timpre); in timer_ker_set_rate()
963 ret = -EINVAL; in timer_ker_set_rate()
965 spin_unlock_irqrestore(tim_ker->lock, flags); in timer_ker_set_rate()
977 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in timer_ker_recalc_rate()
979 timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK; in timer_ker_recalc_rate()
1010 return ERR_PTR(-ENOMEM); in clk_register_cktim()
1018 tim_ker->hw.init = &init; in clk_register_cktim()
1019 tim_ker->lock = lock; in clk_register_cktim()
1020 tim_ker->apbdiv = apbdiv; in clk_register_cktim()
1021 tim_ker->timpre = timpre; in clk_register_cktim()
1023 hw = &tim_ker->hw; in clk_register_cktim()
1043 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; in _clk_register_pll()
1045 return clk_register_pll(dev, cfg->name, cfg->parent_name, in _clk_register_pll()
1046 base + stm_pll_cfg->offset, cfg->flags, lock); in _clk_register_pll()
1059 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; in _clk_register_cktim()
1061 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, in _clk_register_cktim()
1062 cktim_cfg->offset_apbdiv + base, in _clk_register_cktim()
1063 cktim_cfg->offset_timpre + base, lock); in _clk_register_cktim()
1073 cfg->name, in _clk_stm32_register_gate()
1074 cfg->parent_name, in _clk_stm32_register_gate()
1075 cfg->flags, in _clk_stm32_register_gate()
1077 cfg->cfg, in _clk_stm32_register_gate()
1087 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, in _clk_stm32_register_composite()
1088 cfg->num_parents, base, cfg->cfg, in _clk_stm32_register_composite()
1089 cfg->flags, lock); in _clk_stm32_register_composite()
1185 /* STM32 GATE */
1661 DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
1665 GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1667 GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1669 GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
1670 GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1671 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1673 FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1819 PCLK(CEC, "cec", "pclk1", 0, G_CEC),
2013 .compatible = "st,stm32mp1-rcc",
2025 struct clk_hw *hw = ERR_PTR(-ENOENT); in stm32_register_hw_clk()
2027 hws = clk_data->hws; in stm32_register_hw_clk()
2029 if (cfg->func) in stm32_register_hw_clk()
2030 hw = (*cfg->func)(dev, clk_data, base, lock, cfg); in stm32_register_hw_clk()
2033 pr_err("Unable to register %s\n", cfg->name); in stm32_register_hw_clk()
2037 if (cfg->id != NO_ID) in stm32_register_hw_clk()
2038 hws[cfg->id] = hw; in stm32_register_hw_clk()
2056 return -ENODEV; in stm32_rcc_init()
2059 data = match->data; in stm32_rcc_init()
2061 max_binding = data->maxbinding; in stm32_rcc_init()
2066 return -ENOMEM; in stm32_rcc_init()
2068 clk_data->num = max_binding; in stm32_rcc_init()
2070 hws = clk_data->hws; in stm32_rcc_init()
2073 hws[n] = ERR_PTR(-ENOENT); in stm32_rcc_init()
2075 for (n = 0; n < data->num; n++) { in stm32_rcc_init()
2077 &data->cfg[n]); in stm32_rcc_init()
2080 data->cfg[n].name); in stm32_rcc_init()
2108 CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);