Lines Matching refs:gcc
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
357 <&gcc GCC_PCIE_CLKREF_CLK>;
360 resets = <&gcc GCC_PCIE_PHY_BCR>,
361 <&gcc GCC_PCIE_PHY_COM_BCR>,
362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
375 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
388 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
401 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
436 clocks = <&gcc GCC_PRNG_AHB_CLK>;
440 gcc: clock-controller@300000 { label
441 compatible = "qcom,gcc-msm8996";
616 <&gcc GCC_HDMI_CLKREF_CLK>;
633 <&gcc GCC_BIMC_GFX_CLK>,
634 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
726 power-domains = <&gcc AGGRE0_NOC_GDSC>;
735 power-domains = <&gcc PCIE0_GDSC>;
768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
769 <&gcc GCC_PCIE_0_AUX_CLK>,
770 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
771 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
772 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
784 power-domains = <&gcc PCIE1_GDSC>;
820 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
821 <&gcc GCC_PCIE_1_AUX_CLK>,
822 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
823 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
824 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
835 power-domains = <&gcc PCIE2_GDSC>;
870 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
871 <&gcc GCC_PCIE_2_AUX_CLK>,
872 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
873 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
874 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
892 power-domains = <&gcc UFS_GDSC>;
907 <&gcc UFS_AXI_CLK_SRC>,
908 <&gcc GCC_UFS_AXI_CLK>,
909 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
910 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
911 <&gcc GCC_UFS_AHB_CLK>,
912 <&gcc UFS_ICE_CORE_CLK_SRC>,
913 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
914 <&gcc GCC_UFS_ICE_CORE_CLK>,
916 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
917 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
947 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
1145 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1255 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1272 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1273 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1757 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1758 <&gcc GCC_USB30_MASTER_CLK>,
1759 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1760 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1761 <&gcc GCC_USB30_SLEEP_CLK>,
1762 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1764 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1765 <&gcc GCC_USB30_MASTER_CLK>;
1768 power-domains = <&gcc USB30_GDSC>;
1790 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1791 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1792 <&gcc GCC_USB3_CLKREF_CLK>;
1795 resets = <&gcc GCC_USB3_PHY_BCR>,
1796 <&gcc GCC_USB3PHY_PHY_BCR>;
1807 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1817 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1818 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1821 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1831 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1832 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1835 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1851 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1852 <&gcc GCC_SDCC2_APPS_CLK>,
1861 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1862 <&gcc GCC_BLSP1_AHB_CLK>;
1871 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1872 <&gcc GCC_BLSP1_AHB_CLK>;
1886 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1887 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1901 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1902 <&gcc GCC_BLSP2_AHB_CLK>;
1911 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1912 <&gcc GCC_BLSP2_AHB_CLK>;
1921 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1922 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1936 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1937 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1951 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1952 <&gcc GCC_BLSP2_AHB_CLK>;
1969 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1970 <&gcc GCC_USB20_MASTER_CLK>,
1971 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1972 <&gcc GCC_USB20_SLEEP_CLK>,
1973 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1975 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1976 <&gcc GCC_USB20_MASTER_CLK>;
1979 power-domains = <&gcc USB30_GDSC>;
2076 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;