Lines Matching +full:redistributor +full:- +full:stride
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32764>;
31 clock-output-names = "sleep_clk";
36 #address-cells = <2>;
37 #size-cells = <0>;
43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
47 L2_0: l2-cache {
49 cache-level = <2>;
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0>;
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
67 enable-method = "psci";
68 cpu-idle-states = <&CPU_SLEEP_0>;
69 capacity-dmips-mhz = <1024>;
70 next-level-cache = <&L2_1>;
71 L2_1: l2-cache {
73 cache-level = <2>;
81 enable-method = "psci";
82 cpu-idle-states = <&CPU_SLEEP_0>;
83 capacity-dmips-mhz = <1024>;
84 next-level-cache = <&L2_1>;
87 cpu-map {
109 idle-states {
110 entry-method = "psci";
112 CPU_SLEEP_0: cpu-sleep-0 {
113 compatible = "arm,idle-state";
114 idle-state-name = "standalone-power-collapse";
115 arm,psci-suspend-param = <0x00000004>;
116 entry-latency-us = <130>;
117 exit-latency-us = <80>;
118 min-residency-us = <300>;
125 compatible = "qcom,scm-msm8996";
126 qcom,dload-mode = <&tcsr 0x13000>;
131 compatible = "qcom,tcsr-mutex";
133 #hwlock-cells = <1>;
143 compatible = "arm,psci-1.0";
147 reserved-memory {
148 #address-cells = <2>;
149 #size-cells = <2>;
154 no-map;
159 no-map;
164 no-map;
169 no-map;
174 no-map;
177 smem_mem: smem-mem@86000000 {
179 no-map;
184 no-map;
189 no-map;
193 compatible = "qcom,rmtfs-mem";
196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
197 no-map;
199 qcom,client-id = <1>;
204 compatible = "shared-dma-pool";
206 no-map;
210 rpm-glink {
211 compatible = "qcom,glink-rpm";
215 qcom,rpm-msg-ram = <&rpm_msg_ram>;
219 rpm_requests: rpm-requests {
220 compatible = "qcom,rpm-msm8996";
221 qcom,glink-channels = "rpm_requests";
224 compatible = "qcom,rpmcc-msm8996";
225 #clock-cells = <1>;
228 rpmpd: power-controller {
229 compatible = "qcom,msm8996-rpmpd";
230 #power-domain-cells = <1>;
231 operating-points-v2 = <&rpmpd_opp_table>;
233 rpmpd_opp_table: opp-table {
234 compatible = "operating-points-v2";
237 opp-level = <1>;
241 opp-level = <2>;
245 opp-level = <3>;
249 opp-level = <4>;
253 opp-level = <5>;
257 opp-level = <6>;
266 memory-region = <&smem_mem>;
270 smp2p-adsp {
278 qcom,local-pid = <0>;
279 qcom,remote-pid = <2>;
281 smp2p_adsp_out: master-kernel {
282 qcom,entry-name = "master-kernel";
283 #qcom,smem-state-cells = <1>;
286 smp2p_adsp_in: slave-kernel {
287 qcom,entry-name = "slave-kernel";
289 interrupt-controller;
290 #interrupt-cells = <2>;
294 smp2p-modem {
302 qcom,local-pid = <0>;
303 qcom,remote-pid = <1>;
305 modem_smp2p_out: master-kernel {
306 qcom,entry-name = "master-kernel";
307 #qcom,smem-state-cells = <1>;
310 modem_smp2p_in: slave-kernel {
311 qcom,entry-name = "slave-kernel";
313 interrupt-controller;
314 #interrupt-cells = <2>;
318 smp2p-slpi {
326 qcom,local-pid = <0>;
327 qcom,remote-pid = <3>;
329 smp2p_slpi_in: slave-kernel {
330 qcom,entry-name = "slave-kernel";
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 smp2p_slpi_out: master-kernel {
336 qcom,entry-name = "master-kernel";
337 #qcom,smem-state-cells = <1>;
342 #address-cells = <1>;
343 #size-cells = <1>;
345 compatible = "simple-bus";
348 compatible = "qcom,msm8996-qmp-pcie-phy";
350 #clock-cells = <1>;
351 #address-cells = <1>;
352 #size-cells = <1>;
358 clock-names = "aux", "cfg_ahb", "ref";
363 reset-names = "phy", "common", "cfg";
370 #phy-cells = <0>;
372 clock-output-names = "pcie_0_pipe_clk_src";
374 clock-names = "pipe0";
376 reset-names = "lane0";
383 #phy-cells = <0>;
385 clock-output-names = "pcie_1_pipe_clk_src";
387 clock-names = "pipe1";
389 reset-names = "lane1";
396 #phy-cells = <0>;
398 clock-output-names = "pcie_2_pipe_clk_src";
400 clock-names = "pipe2";
402 reset-names = "lane2";
407 compatible = "qcom,rpm-msg-ram";
414 #address-cells = <1>;
415 #size-cells = <1>;
434 compatible = "qcom,prng-ee";
437 clock-names = "core";
440 gcc: clock-controller@300000 {
441 compatible = "qcom,gcc-msm8996";
442 #clock-cells = <1>;
443 #reset-cells = <1>;
444 #power-domain-cells = <1>;
448 clock-names = "cxo2";
451 tsens0: thermal-sensor@4a9000 {
452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
458 interrupt-names = "uplow", "critical";
459 #thermal-sensor-cells = <1>;
462 tsens1: thermal-sensor@4ad000 {
463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
469 interrupt-names = "uplow", "critical";
470 #thermal-sensor-cells = <1>;
479 compatible = "qcom,tcsr-msm8996", "syscon";
483 mmcc: clock-controller@8c0000 {
484 compatible = "qcom,mmcc-msm8996";
485 #clock-cells = <1>;
486 #reset-cells = <1>;
487 #power-domain-cells = <1>;
489 assigned-clocks = <&mmcc MMPLL9_PLL>,
494 assigned-clock-rates = <624000000>,
507 reg-names = "mdss_phys",
511 power-domains = <&mmcc MDSS_GDSC>;
514 interrupt-controller;
515 #interrupt-cells = <1>;
518 clock-names = "iface";
520 #address-cells = <1>;
521 #size-cells = <1>;
527 reg-names = "mdp_phys";
529 interrupt-parent = <&mdss>;
537 clock-names = "iface",
546 #address-cells = <1>;
547 #size-cells = <0>;
552 remote-endpoint = <&hdmi_in>;
558 hdmi: hdmi-tx@9a0000 {
559 compatible = "qcom,hdmi-tx-8996";
563 reg-names = "core_physical",
567 interrupt-parent = <&mdss>;
575 clock-names =
583 phy-names = "hdmi_phy";
584 #sound-dai-cells = <1>;
587 #address-cells = <1>;
588 #size-cells = <0>;
593 remote-endpoint = <&mdp5_intf3_out>;
599 hdmi_phy: hdmi-phy@9a0600 {
600 #phy-cells = <0>;
601 compatible = "qcom,hdmi-phy-8996";
608 reg-names = "hdmi_pll",
617 clock-names = "iface",
622 compatible = "qcom,adreno-530.2", "qcom,adreno";
623 #stream-id-cells = <16>;
626 reg-names = "kgsl_3d0_reg_memory";
636 clock-names = "core",
642 power-domains = <&mmcc GPU_GX_GDSC>;
645 nvmem-cells = <&gpu_speed_bin>;
646 nvmem-cell-names = "speed_bin";
648 qcom,gpu-quirk-two-pass-use-wfi;
649 qcom,gpu-quirk-fault-detect-mask;
651 operating-points-v2 = <&gpu_opp_table>;
653 gpu_opp_table: opp-table {
654 compatible ="operating-points-v2";
661 opp-624000000 {
662 opp-hz = /bits/ 64 <624000000>;
663 opp-supported-hw = <0x01>;
665 opp-560000000 {
666 opp-hz = /bits/ 64 <560000000>;
667 opp-supported-hw = <0x01>;
669 opp-510000000 {
670 opp-hz = /bits/ 64 <510000000>;
671 opp-supported-hw = <0xFF>;
673 opp-401800000 {
674 opp-hz = /bits/ 64 <401800000>;
675 opp-supported-hw = <0xFF>;
677 opp-315000000 {
678 opp-hz = /bits/ 64 <315000000>;
679 opp-supported-hw = <0xFF>;
681 opp-214000000 {
682 opp-hz = /bits/ 64 <214000000>;
683 opp-supported-hw = <0xFF>;
685 opp-133000000 {
686 opp-hz = /bits/ 64 <133000000>;
687 opp-supported-hw = <0xFF>;
691 zap-shader {
692 memory-region = <&zap_shader_region>;
697 compatible = "qcom,msm8996-pinctrl";
700 gpio-controller;
701 gpio-ranges = <&msmgpio 0 0 150>;
702 #gpio-cells = <2>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
708 compatible = "qcom,spmi-pmic-arb";
714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
715 interrupt-names = "periph_irq";
719 #address-cells = <2>;
720 #size-cells = <0>;
721 interrupt-controller;
722 #interrupt-cells = <4>;
726 power-domains = <&gcc AGGRE0_NOC_GDSC>;
727 compatible = "simple-pm-bus";
728 #address-cells = <1>;
729 #size-cells = <1>;
733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
735 power-domains = <&gcc PCIE0_GDSC>;
736 bus-range = <0x00 0xff>;
737 num-lanes = <1>;
743 reg-names = "parf", "dbi", "elbi","config";
746 phy-names = "pciephy";
748 #address-cells = <3>;
749 #size-cells = <2>;
754 interrupt-names = "msi";
755 #interrupt-cells = <1>;
756 interrupt-map-mask = <0 0 0 0x7>;
757 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
762 pinctrl-names = "default", "sleep";
763 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
764 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
766 linux,pci-domain = <0>;
774 clock-names = "pipe",
783 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
784 power-domains = <&gcc PCIE1_GDSC>;
785 bus-range = <0x00 0xff>;
786 num-lanes = <1>;
795 reg-names = "parf", "dbi", "elbi","config";
798 phy-names = "pciephy";
800 #address-cells = <3>;
801 #size-cells = <2>;
806 interrupt-names = "msi";
807 #interrupt-cells = <1>;
808 interrupt-map-mask = <0 0 0 0x7>;
809 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
814 pinctrl-names = "default", "sleep";
815 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
816 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
818 linux,pci-domain = <1>;
826 clock-names = "pipe",
834 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
835 power-domains = <&gcc PCIE2_GDSC>;
836 bus-range = <0x00 0xff>;
837 num-lanes = <1>;
844 reg-names = "parf", "dbi", "elbi","config";
847 phy-names = "pciephy";
849 #address-cells = <3>;
850 #size-cells = <2>;
857 interrupt-names = "msi";
858 #interrupt-cells = <1>;
859 interrupt-map-mask = <0 0 0 0x7>;
860 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
865 pinctrl-names = "default", "sleep";
866 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
867 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
869 linux,pci-domain = <2>;
876 clock-names = "pipe",
890 phy-names = "ufsphy";
892 power-domains = <&gcc UFS_GDSC>;
894 clock-names =
918 freq-table-hz =
931 lanes-per-direction = <1>;
932 #reset-cells = <1>;
941 compatible = "qcom,msm8996-qmp-ufs-phy";
943 #address-cells = <1>;
944 #size-cells = <1>;
948 clock-names = "ref";
951 reset-names = "ufsphy";
958 #phy-cells = <0>;
963 compatible = "qcom,msm8996-camss";
978 reg-names = "csiphy0",
1002 interrupt-names = "csiphy0",
1012 power-domains = <&mmcc VFE0_GDSC>,
1050 clock-names = "top_ahb",
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1098 compatible = "qcom,msm8996-cci";
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1103 power-domains = <&mmcc CAMSS_GDSC>;
1108 clock-names = "camss_top_ahb",
1112 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1114 assigned-clock-rates = <80000000>, <37500000>;
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&cci0_default &cci1_default>;
1119 cci_i2c0: i2c-bus@0 {
1121 clock-frequency = <400000>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1126 cci_i2c1: i2c-bus@1 {
1128 clock-frequency = <400000>;
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1135 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1138 #global-interrupts = <1>;
1142 #iommu-cells = <1>;
1146 clock-names = "iface", "bus";
1148 power-domains = <&mmcc GPU_GDSC>;
1151 video-codec@c00000 {
1152 compatible = "qcom,msm8996-venus";
1155 power-domains = <&mmcc VENUS_GDSC>;
1160 clock-names = "core", "iface", "bus", "mbus";
1181 memory-region = <&venus_region>;
1184 video-decoder {
1185 compatible = "venus-decoder";
1187 clock-names = "core";
1188 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1191 video-encoder {
1192 compatible = "venus-encoder";
1194 clock-names = "core";
1195 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1200 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1203 #global-interrupts = <1>;
1207 #iommu-cells = <1>;
1210 clock-names = "iface", "bus";
1212 power-domains = <&mmcc MDSS_GDSC>;
1216 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1218 #global-interrupts = <1>;
1227 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1230 clock-names = "iface", "bus";
1231 #iommu-cells = <1>;
1236 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1239 #global-interrupts = <1>;
1243 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1246 clock-names = "iface",
1248 #iommu-cells = <1>;
1252 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1254 #iommu-cells = <1>;
1255 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1257 #global-interrupts = <1>;
1274 clock-names = "iface", "bus";
1278 compatible = "arm,coresight-stm", "arm,primecell";
1281 reg-names = "stm-base", "stm-stimulus-base";
1284 clock-names = "apb_pclk", "atclk";
1286 out-ports {
1289 remote-endpoint =
1297 compatible = "arm,coresight-tpiu", "arm,primecell";
1301 clock-names = "apb_pclk", "atclk";
1303 in-ports {
1306 remote-endpoint =
1314 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1318 clock-names = "apb_pclk", "atclk";
1320 in-ports {
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1327 remote-endpoint =
1333 out-ports {
1336 remote-endpoint =
1344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1348 clock-names = "apb_pclk", "atclk";
1350 in-ports {
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1357 remote-endpoint =
1363 out-ports {
1366 remote-endpoint =
1374 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1378 clock-names = "apb_pclk", "atclk";
1381 out-ports {
1384 remote-endpoint =
1392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1396 clock-names = "apb_pclk", "atclk";
1398 in-ports {
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1405 remote-endpoint =
1413 remote-endpoint =
1421 remote-endpoint =
1427 out-ports {
1430 remote-endpoint =
1438 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1442 clock-names = "apb_pclk", "atclk";
1444 in-ports {
1447 remote-endpoint =
1453 out-ports {
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1460 remote-endpoint =
1468 remote-endpoint =
1476 compatible = "arm,coresight-tmc", "arm,primecell";
1480 clock-names = "apb_pclk", "atclk";
1482 in-ports {
1485 remote-endpoint =
1491 out-ports {
1494 remote-endpoint =
1502 compatible = "arm,coresight-tmc", "arm,primecell";
1506 clock-names = "apb_pclk", "atclk";
1507 arm,scatter-gather;
1509 in-ports {
1512 remote-endpoint =
1520 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1524 clock-names = "apb_pclk";
1530 compatible = "arm,coresight-etm4x", "arm,primecell";
1534 clock-names = "apb_pclk", "atclk";
1538 out-ports {
1541 remote-endpoint =
1549 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1553 clock-names = "apb_pclk";
1559 compatible = "arm,coresight-etm4x", "arm,primecell";
1563 clock-names = "apb_pclk", "atclk";
1567 out-ports {
1570 remote-endpoint =
1578 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1582 clock-names = "apb_pclk", "atclk";
1584 in-ports {
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1591 remote-endpoint = <&etm0_out>;
1598 remote-endpoint = <&etm1_out>;
1603 out-ports {
1606 remote-endpoint =
1614 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1618 clock-names = "apb_pclk";
1624 compatible = "arm,coresight-etm4x", "arm,primecell";
1628 clock-names = "apb_pclk", "atclk";
1632 out-ports {
1635 remote-endpoint =
1643 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1647 clock-names = "apb_pclk";
1653 compatible = "arm,coresight-etm4x", "arm,primecell";
1657 clock-names = "apb_pclk", "atclk";
1661 out-ports {
1664 remote-endpoint =
1672 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1676 clock-names = "apb_pclk", "atclk";
1678 in-ports {
1679 #address-cells = <1>;
1680 #size-cells = <0>;
1685 remote-endpoint = <&etm2_out>;
1692 remote-endpoint = <&etm3_out>;
1697 out-ports {
1700 remote-endpoint =
1708 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1712 clock-names = "apb_pclk", "atclk";
1714 in-ports {
1715 #address-cells = <1>;
1716 #size-cells = <0>;
1721 remote-endpoint =
1729 remote-endpoint =
1735 out-ports {
1738 remote-endpoint =
1744 kryocc: clock-controller@6400000 {
1745 compatible = "qcom,apcc-msm8996";
1747 #clock-cells = <1>;
1751 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1753 #address-cells = <1>;
1754 #size-cells = <1>;
1764 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1766 assigned-clock-rates = <19200000>, <120000000>;
1768 power-domains = <&gcc USB30_GDSC>;
1776 phy-names = "usb2-phy", "usb3-phy";
1783 compatible = "qcom,msm8996-qmp-usb3-phy";
1785 #clock-cells = <1>;
1786 #address-cells = <1>;
1787 #size-cells = <1>;
1793 clock-names = "aux", "cfg_ahb", "ref";
1797 reset-names = "phy", "common";
1804 #phy-cells = <0>;
1806 clock-output-names = "usb3_phy_pipe_clk_src";
1808 clock-names = "pipe0";
1813 compatible = "qcom,msm8996-qusb2-phy";
1815 #phy-cells = <0>;
1819 clock-names = "cfg_ahb", "ref";
1822 nvmem-cells = <&qusb2p_hstx_trim>;
1827 compatible = "qcom,msm8996-qusb2-phy";
1829 #phy-cells = <0>;
1833 clock-names = "cfg_ahb", "ref";
1836 nvmem-cells = <&qusb2s_hstx_trim>;
1842 compatible = "qcom,sdhci-msm-v4";
1844 reg-names = "hc_mem", "core_mem";
1848 interrupt-names = "hc_irq", "pwr_irq";
1850 clock-names = "iface", "core", "xo";
1854 bus-width = <4>;
1858 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 clock-names = "core", "iface";
1868 compatible = "qcom,spi-qup-v2.2.1";
1873 clock-names = "core", "iface";
1874 pinctrl-names = "default", "sleep";
1875 pinctrl-0 = <&blsp1_spi0_default>;
1876 pinctrl-1 = <&blsp1_spi0_sleep>;
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1883 compatible = "qcom,i2c-qup-v2.2.1";
1888 clock-names = "iface", "core";
1889 pinctrl-names = "default", "sleep";
1890 pinctrl-0 = <&blsp1_i2c2_default>;
1891 pinctrl-1 = <&blsp1_i2c2_sleep>;
1892 #address-cells = <1>;
1893 #size-cells = <0>;
1898 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1903 clock-names = "core", "iface";
1908 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1913 clock-names = "core", "iface";
1918 compatible = "qcom,i2c-qup-v2.2.1";
1923 clock-names = "iface", "core";
1924 pinctrl-names = "default", "sleep";
1925 pinctrl-0 = <&blsp2_i2c0_default>;
1926 pinctrl-1 = <&blsp2_i2c0_sleep>;
1927 #address-cells = <1>;
1928 #size-cells = <0>;
1933 compatible = "qcom,i2c-qup-v2.2.1";
1938 clock-names = "iface", "core";
1939 pinctrl-names = "default", "sleep";
1940 pinctrl-0 = <&blsp2_i2c1_default>;
1941 pinctrl-1 = <&blsp2_i2c1_sleep>;
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1948 compatible = "qcom,spi-qup-v2.2.1";
1953 clock-names = "core", "iface";
1954 pinctrl-names = "default", "sleep";
1955 pinctrl-0 = <&blsp2_spi5_default>;
1956 pinctrl-1 = <&blsp2_spi5_sleep>;
1957 #address-cells = <1>;
1958 #size-cells = <0>;
1963 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1965 #address-cells = <1>;
1966 #size-cells = <1>;
1975 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1977 assigned-clock-rates = <19200000>, <60000000>;
1979 power-domains = <&gcc USB30_GDSC>;
1987 phy-names = "usb2-phy";
1994 compatible = "qcom,bam-v1.7.0";
1995 qcom,controlled-remotely;
1997 num-channels = <31>;
1999 #dma-cells = <1>;
2001 qcom,num-ees = <2>;
2005 compatible = "qcom,slim-ngd-v1.5.0";
2007 reg-names = "ctrl";
2011 dma-names = "rx", "tx", "tx2", "rx2";
2012 #address-cells = <1>;
2013 #size-cells = <0>;
2016 #address-cells = <1>;
2017 #size-cells = <1>;
2019 tasha_ifd: tas-ifd {
2025 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2026 pinctrl-names = "default";
2031 interrupt-parent = <&msmgpio>;
2034 interrupt-names = "intr1", "intr2";
2035 interrupt-controller;
2036 #interrupt-cells = <1>;
2037 reset-gpios = <&msmgpio 64 0>;
2039 slim-ifc-dev = <&tasha_ifd>;
2041 #sound-dai-cells = <1>;
2047 compatible = "qcom,msm8996-adsp-pil";
2050 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2055 interrupt-names = "wdog", "fatal", "ready",
2056 "handover", "stop-ack";
2059 clock-names = "xo";
2061 memory-region = <&adsp_region>;
2063 qcom,smem-states = <&smp2p_adsp_out 0>;
2064 qcom,smem-state-names = "stop";
2066 smd-edge {
2071 qcom,smd-edge = <1>;
2072 qcom,remote-pid = <2>;
2073 #address-cells = <1>;
2074 #size-cells = <0>;
2076 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2077 compatible = "qcom,apr-v2";
2078 qcom,smd-channels = "apr_audio_svc";
2079 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2080 #address-cells = <1>;
2081 #size-cells = <0>;
2092 compatible = "qcom,q6afe-dais";
2093 #address-cells = <1>;
2094 #size-cells = <0>;
2095 #sound-dai-cells = <1>;
2106 compatible = "qcom,q6asm-dais";
2107 #address-cells = <1>;
2108 #size-cells = <0>;
2109 #sound-dai-cells = <1>;
2118 compatible = "qcom,q6adm-routing";
2119 #sound-dai-cells = <0>;
2128 compatible = "qcom,msm8996-apcs-hmss-global";
2131 #mbox-cells = <1>;
2135 #address-cells = <1>;
2136 #size-cells = <1>;
2138 compatible = "arm,armv7-timer-mem";
2140 clock-frequency = <19200000>;
2143 frame-number = <0>;
2151 frame-number = <1>;
2158 frame-number = <2>;
2165 frame-number = <3>;
2172 frame-number = <4>;
2179 frame-number = <5>;
2186 frame-number = <6>;
2198 intc: interrupt-controller@9bc0000 {
2199 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
2200 #interrupt-cells = <3>;
2201 interrupt-controller;
2202 #redistributor-regions = <1>;
2203 redistributor-stride = <0x0 0x40000>;
2213 thermal-zones {
2214 cpu0-thermal {
2215 polling-delay-passive = <250>;
2216 polling-delay = <1000>;
2218 thermal-sensors = <&tsens0 3>;
2221 cpu0_alert0: trip-point0 {
2235 cpu1-thermal {
2236 polling-delay-passive = <250>;
2237 polling-delay = <1000>;
2239 thermal-sensors = <&tsens0 5>;
2242 cpu1_alert0: trip-point0 {
2256 cpu2-thermal {
2257 polling-delay-passive = <250>;
2258 polling-delay = <1000>;
2260 thermal-sensors = <&tsens0 8>;
2263 cpu2_alert0: trip-point0 {
2277 cpu3-thermal {
2278 polling-delay-passive = <250>;
2279 polling-delay = <1000>;
2281 thermal-sensors = <&tsens0 10>;
2284 cpu3_alert0: trip-point0 {
2298 gpu-thermal-top {
2299 polling-delay-passive = <250>;
2300 polling-delay = <1000>;
2302 thermal-sensors = <&tsens1 6>;
2305 gpu1_alert0: trip-point0 {
2313 gpu-thermal-bottom {
2314 polling-delay-passive = <250>;
2315 polling-delay = <1000>;
2317 thermal-sensors = <&tsens1 7>;
2320 gpu2_alert0: trip-point0 {
2328 m4m-thermal {
2329 polling-delay-passive = <250>;
2330 polling-delay = <1000>;
2332 thermal-sensors = <&tsens0 1>;
2335 m4m_alert0: trip-point0 {
2343 l3-or-venus-thermal {
2344 polling-delay-passive = <250>;
2345 polling-delay = <1000>;
2347 thermal-sensors = <&tsens0 2>;
2350 l3_or_venus_alert0: trip-point0 {
2358 cluster0-l2-thermal {
2359 polling-delay-passive = <250>;
2360 polling-delay = <1000>;
2362 thermal-sensors = <&tsens0 7>;
2365 cluster0_l2_alert0: trip-point0 {
2373 cluster1-l2-thermal {
2374 polling-delay-passive = <250>;
2375 polling-delay = <1000>;
2377 thermal-sensors = <&tsens0 12>;
2380 cluster1_l2_alert0: trip-point0 {
2388 camera-thermal {
2389 polling-delay-passive = <250>;
2390 polling-delay = <1000>;
2392 thermal-sensors = <&tsens1 1>;
2395 camera_alert0: trip-point0 {
2403 q6-dsp-thermal {
2404 polling-delay-passive = <250>;
2405 polling-delay = <1000>;
2407 thermal-sensors = <&tsens1 2>;
2410 q6_dsp_alert0: trip-point0 {
2418 mem-thermal {
2419 polling-delay-passive = <250>;
2420 polling-delay = <1000>;
2422 thermal-sensors = <&tsens1 3>;
2425 mem_alert0: trip-point0 {
2433 modemtx-thermal {
2434 polling-delay-passive = <250>;
2435 polling-delay = <1000>;
2437 thermal-sensors = <&tsens1 4>;
2440 modemtx_alert0: trip-point0 {
2450 compatible = "arm,armv8-timer";
2457 #include "msm8996-pins.dtsi"