Lines Matching full:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
483 mmcc: clock-controller@8c0000 { label
484 compatible = "qcom,mmcc-msm8996";
489 assigned-clocks = <&mmcc MMPLL9_PLL>,
490 <&mmcc MMPLL1_PLL>,
491 <&mmcc MMPLL3_PLL>,
492 <&mmcc MMPLL4_PLL>,
493 <&mmcc MMPLL5_PLL>;
511 power-domains = <&mmcc MDSS_GDSC>;
517 clocks = <&mmcc MDSS_AHB_CLK>;
532 clocks = <&mmcc MDSS_AHB_CLK>,
533 <&mmcc MDSS_AXI_CLK>,
534 <&mmcc MDSS_MDP_CLK>,
535 <&mmcc SMMU_MDP_AXI_CLK>,
536 <&mmcc MDSS_VSYNC_CLK>;
570 clocks = <&mmcc MDSS_MDP_CLK>,
571 <&mmcc MDSS_AHB_CLK>,
572 <&mmcc MDSS_HDMI_CLK>,
573 <&mmcc MDSS_HDMI_AHB_CLK>,
574 <&mmcc MDSS_EXTPCLK_CLK>;
615 clocks = <&mmcc MDSS_AHB_CLK>,
630 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
631 <&mmcc GPU_AHB_CLK>,
632 <&mmcc GPU_GX_RBBMTIMER_CLK>,
642 power-domains = <&mmcc GPU_GX_GDSC>;
1012 power-domains = <&mmcc VFE0_GDSC>,
1013 <&mmcc VFE1_GDSC>;
1014 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1015 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1016 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1017 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1018 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1019 <&mmcc CAMSS_CSI0_AHB_CLK>,
1020 <&mmcc CAMSS_CSI0_CLK>,
1021 <&mmcc CAMSS_CSI0PHY_CLK>,
1022 <&mmcc CAMSS_CSI0PIX_CLK>,
1023 <&mmcc CAMSS_CSI0RDI_CLK>,
1024 <&mmcc CAMSS_CSI1_AHB_CLK>,
1025 <&mmcc CAMSS_CSI1_CLK>,
1026 <&mmcc CAMSS_CSI1PHY_CLK>,
1027 <&mmcc CAMSS_CSI1PIX_CLK>,
1028 <&mmcc CAMSS_CSI1RDI_CLK>,
1029 <&mmcc CAMSS_CSI2_AHB_CLK>,
1030 <&mmcc CAMSS_CSI2_CLK>,
1031 <&mmcc CAMSS_CSI2PHY_CLK>,
1032 <&mmcc CAMSS_CSI2PIX_CLK>,
1033 <&mmcc CAMSS_CSI2RDI_CLK>,
1034 <&mmcc CAMSS_CSI3_AHB_CLK>,
1035 <&mmcc CAMSS_CSI3_CLK>,
1036 <&mmcc CAMSS_CSI3PHY_CLK>,
1037 <&mmcc CAMSS_CSI3PIX_CLK>,
1038 <&mmcc CAMSS_CSI3RDI_CLK>,
1039 <&mmcc CAMSS_AHB_CLK>,
1040 <&mmcc CAMSS_VFE0_CLK>,
1041 <&mmcc CAMSS_CSI_VFE0_CLK>,
1042 <&mmcc CAMSS_VFE0_AHB_CLK>,
1043 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1044 <&mmcc CAMSS_VFE1_CLK>,
1045 <&mmcc CAMSS_CSI_VFE1_CLK>,
1046 <&mmcc CAMSS_VFE1_AHB_CLK>,
1047 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1048 <&mmcc CAMSS_VFE_AHB_CLK>,
1049 <&mmcc CAMSS_VFE_AXI_CLK>;
1103 power-domains = <&mmcc CAMSS_GDSC>;
1104 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1105 <&mmcc CAMSS_CCI_AHB_CLK>,
1106 <&mmcc CAMSS_CCI_CLK>,
1107 <&mmcc CAMSS_AHB_CLK>;
1112 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1113 <&mmcc CAMSS_CCI_CLK>;
1144 clocks = <&mmcc GPU_AHB_CLK>,
1148 power-domains = <&mmcc GPU_GDSC>;
1155 power-domains = <&mmcc VENUS_GDSC>;
1156 clocks = <&mmcc VIDEO_CORE_CLK>,
1157 <&mmcc VIDEO_AHB_CLK>,
1158 <&mmcc VIDEO_AXI_CLK>,
1159 <&mmcc VIDEO_MAXI_CLK>;
1186 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1188 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1193 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1195 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1208 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1209 <&mmcc SMMU_MDP_AXI_CLK>;
1212 power-domains = <&mmcc MDSS_GDSC>;
1227 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1228 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1229 <&mmcc SMMU_VIDEO_AXI_CLK>;
1243 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1244 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1245 <&mmcc SMMU_VFE_AXI_CLK>;