Lines Matching +full:0 +full:x10023c80
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0>;
100 xusbxti: clock-0 {
102 clock-frequency = <0>;
103 #clock-cells = <0>;
109 clock-frequency = <0>;
110 #clock-cells = <0>;
116 clock-frequency = <0>;
117 #clock-cells = <0>;
135 reg = <0x02020000 0x40000>;
138 ranges = <0 0x02020000 0x40000>;
140 smp-sram@0 {
142 reg = <0x0 0x1000>;
147 reg = <0x3f000 0x1000>;
153 reg = <0x10000000 0x100>;
158 reg = <0x10010000 0x400>;
163 reg = <0x10020000 0x4000>;
180 reg = <0x10023C00 0x20>;
181 #power-domain-cells = <0>;
187 reg = <0x10023C40 0x20>;
188 #power-domain-cells = <0>;
194 reg = <0x10023C60 0x20>;
195 #power-domain-cells = <0>;
201 reg = <0x10023C80 0x20>;
202 #power-domain-cells = <0>;
208 reg = <0x10023CA0 0x20>;
209 #power-domain-cells = <0>;
215 reg = <0x10030000 0x20000>;
225 reg = <0x105C0000 0x2000>;
231 reg = <0x10070000 0x100>;
240 reg = <0x100C0000 0x100>;
244 #thermal-sensor-cells = <0>;
252 reg = <0x10481000 0x1000>,
253 <0x10482000 0x2000>,
254 <0x10484000 0x2000>,
255 <0x10486000 0x2000>;
262 reg = <0x10050000 0x800>;
277 reg = <0x11000000 0x1000>;
288 reg = <0x11400000 0x1000>;
294 reg = <0x11830000 0x1000>;
300 assigned-clock-rates = <0>, <150000000>;
308 reg = <0x11a60000 0x1000>;
313 #iommu-cells = <0>;
318 reg = <0x11c00000 0x30000>;
333 reg = <0x11C80000 0x10000>;
335 samsung,phy-type = <0>;
342 #size-cells = <0>;
348 reg = <0x11e20000 0x1000>;
353 #iommu-cells = <0>;
358 reg = <0x12480000 0x20000>;
362 phys = <&exynos_usbphy 0>;
369 reg = <0x12510000 0x1000>;
373 fifo-depth = <0x80>;
375 #size-cells = <0>;
381 reg = <0x12520000 0x1000>;
385 fifo-depth = <0x80>;
387 #size-cells = <0>;
393 reg = <0x12530000 0x1000>;
397 fifo-depth = <0x80>;
399 #size-cells = <0>;
405 reg = <0x125B0000 0x100>;
415 reg = <0x12680000 0x1000>;
426 reg = <0x12690000 0x1000>;
437 reg = <0x126C0000 0x100>;
449 reg = <0x13000000 0x10000>;
482 reg = <0x13400000 0x10000>;
492 reg = <0x13620000 0x1000>;
497 #iommu-cells = <0>;
502 reg = <0x13800000 0x100>;
507 pinctrl-0 = <&uart0_data &uart0_fctl>;
513 reg = <0x13810000 0x100>;
518 pinctrl-0 = <&uart1_data>;
524 reg = <0x13820000 0x100>;
529 pinctrl-0 = <&uart2_data>;
535 #size-cells = <0>;
537 reg = <0x13860000 0x100>;
542 pinctrl-0 = <&i2c0_bus>;
548 #size-cells = <0>;
550 reg = <0x13870000 0x100>;
555 pinctrl-0 = <&i2c1_bus>;
561 #size-cells = <0>;
563 reg = <0x13880000 0x100>;
568 pinctrl-0 = <&i2c2_bus>;
574 #size-cells = <0>;
576 reg = <0x13890000 0x100>;
581 pinctrl-0 = <&i2c3_bus>;
587 #size-cells = <0>;
589 reg = <0x138A0000 0x100>;
594 pinctrl-0 = <&i2c4_bus>;
600 #size-cells = <0>;
602 reg = <0x138B0000 0x100>;
607 pinctrl-0 = <&i2c5_bus>;
613 #size-cells = <0>;
615 reg = <0x138C0000 0x100>;
620 pinctrl-0 = <&i2c6_bus>;
626 #size-cells = <0>;
628 reg = <0x138D0000 0x100>;
633 pinctrl-0 = <&i2c7_bus>;
639 reg = <0x13920000 0x100>;
644 #size-cells = <0>;
647 samsung,spi-src-clk = <0>;
649 pinctrl-0 = <&spi0_bus>;
655 reg = <0x13930000 0x100>;
660 #size-cells = <0>;
663 samsung,spi-src-clk = <0>;
665 pinctrl-0 = <&spi1_bus>;
671 reg = <0x13970000 0x100>;
677 pinctrl-0 = <&i2s2_bus>;
684 reg = <0x139D0000 0x1000>;
696 reg = <0x106a0000 0x2000>;
702 reg = <0x106b0000 0x2000>;
708 reg = <0x106c0000 0x2000>;
714 reg = <0x112a0000 0x2000>;
722 reg = <0x116a0000 0x2000>;
730 reg = <0x11ac0000 0x2000>;
738 reg = <0x11e40000 0x2000>;
746 reg = <0x12630000 0x2000>;
754 reg = <0x13220000 0x2000>;
762 reg = <0x13660000 0x2000>;