Lines Matching full:topckgen
57 <&topckgen CLK_TOP_UNIVPLL_D2>,
58 <&topckgen CLK_TOP_CCI400_SEL>,
59 <&topckgen CLK_TOP_VDEC_SEL>,
60 <&topckgen CLK_TOP_VCODECPLL>,
62 <&topckgen CLK_TOP_VENC_LT_SEL>,
63 <&topckgen CLK_TOP_VCODECPLL_370P5>;
72 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
73 <&topckgen CLK_TOP_CCI400_SEL>,
74 <&topckgen CLK_TOP_VDEC_SEL>,
77 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
78 <&topckgen CLK_TOP_UNIVPLL_D2>,
79 <&topckgen CLK_TOP_VCODECPLL>;
112 clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
113 <&topckgen CLK_TOP_VENC_SEL>,
114 <&topckgen CLK_TOP_UNIVPLL1_D2>,
115 <&topckgen CLK_TOP_VENC_LT_SEL>;
120 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
121 <&topckgen CLK_TOP_VENC_LT_SEL>;
122 assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
123 <&topckgen CLK_TOP_UNIVPLL1_D2>;