122 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,  in qed_mcp_attn_cb()
236 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_grc_attn_cb()
358 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_pglub_rbc_attn_cb()
689 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);  in qed_int_assertion()
701 		qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,  in qed_int_assertion()
783 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));  in qed_int_deassertion_aeu_bit()
824 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);  in qed_int_deassertion_parity()
973 	qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);  in qed_int_deassertion()
1178 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,  in qed_int_sb_attn_setup()
1180 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,  in qed_int_sb_attn_setup()
1327 		qed_wr(p_hwfn, p_ptt,  in qed_int_cau_conf_pi()
1673 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);  in qed_int_igu_enable_int()
1681 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);  in qed_int_igu_enable_attn()
1682 	qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable_attn()
1683 	qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable_attn()
1684 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);  in qed_int_igu_enable_attn()
1690 	qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);  in qed_int_igu_enable_attn()
1723 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);  in qed_int_igu_disable_int()
1746 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);  in qed_int_igu_cleanup_sb()
1750 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);  in qed_int_igu_cleanup_sb()
1817 		qed_wr(p_hwfn, p_ptt,  in qed_int_igu_init_pure_rt_single()
1833 	qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);  in qed_int_igu_init_pure_rt()
1973 			qed_wr(p_hwfn, p_ptt,  in qed_int_igu_reset_cam()