1168 				  struct qed_ptt *p_ptt)  in qed_int_sb_attn_setup()  argument
1178 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,  in qed_int_sb_attn_setup()
1180 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,  in qed_int_sb_attn_setup()
1185 				 struct qed_ptt *p_ptt,  in qed_int_sb_attn_init()  argument
1219 	qed_int_sb_attn_setup(p_hwfn, p_ptt);  in qed_int_sb_attn_init()
1223 				 struct qed_ptt *p_ptt)  in qed_int_sb_attn_alloc()  argument
1247 	qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);  in qed_int_sb_attn_alloc()
1304 				struct qed_ptt *p_ptt,  in qed_int_cau_conf_pi()  argument
1327 		qed_wr(p_hwfn, p_ptt,  in qed_int_cau_conf_pi()
1338 			 struct qed_ptt *p_ptt,  in qed_int_cau_conf_sb()  argument
1351 		qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,  in qed_int_cau_conf_sb()
1354 		qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,  in qed_int_cau_conf_sb()
1384 		qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,  in qed_int_cau_conf_sb()
1395 			qed_int_cau_conf_pi(p_hwfn, p_ptt,  in qed_int_cau_conf_sb()
1404 		      struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)  in qed_int_sb_setup()  argument
1411 		qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,  in qed_int_sb_setup()
1478 		    struct qed_ptt *p_ptt,  in qed_int_sb_init()  argument
1521 	qed_int_sb_setup(p_hwfn, p_ptt, sb_info);  in qed_int_sb_init()
1577 static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)  in qed_int_sp_sb_alloc()  argument
1599 	qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,  in qed_int_sp_sb_alloc()
1650 			    struct qed_ptt *p_ptt, enum qed_int_mode int_mode)  in qed_int_igu_enable_int()  argument
1673 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);  in qed_int_igu_enable_int()
1677 				    struct qed_ptt *p_ptt)  in qed_int_igu_enable_attn()  argument
1681 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);  in qed_int_igu_enable_attn()
1682 	qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable_attn()
1683 	qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);  in qed_int_igu_enable_attn()
1684 	qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);  in qed_int_igu_enable_attn()
1690 	qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);  in qed_int_igu_enable_attn()
1695 		   struct qed_ptt *p_ptt, enum qed_int_mode int_mode)  in qed_int_igu_enable()  argument
1699 	qed_int_igu_enable_attn(p_hwfn, p_ptt);  in qed_int_igu_enable()
1710 	qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);  in qed_int_igu_enable()
1716 void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)  in qed_int_igu_disable_int()  argument
1723 	qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);  in qed_int_igu_disable_int()
1728 				   struct qed_ptt *p_ptt,  in qed_int_igu_cleanup_sb()  argument
1746 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);  in qed_int_igu_cleanup_sb()
1750 	qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);  in qed_int_igu_cleanup_sb()
1763 		val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);  in qed_int_igu_cleanup_sb()
1778 				     struct qed_ptt *p_ptt,  in qed_int_igu_init_pure_rt_single()  argument
1793 		qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);  in qed_int_igu_init_pure_rt_single()
1796 	qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);  in qed_int_igu_init_pure_rt_single()
1802 		val = qed_rd(p_hwfn, p_ptt,  in qed_int_igu_init_pure_rt_single()
1817 		qed_wr(p_hwfn, p_ptt,  in qed_int_igu_init_pure_rt_single()
1822 			      struct qed_ptt *p_ptt,  in qed_int_igu_init_pure_rt()  argument
1830 	val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);  in qed_int_igu_init_pure_rt()
1833 	qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);  in qed_int_igu_init_pure_rt()
1844 		qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,  in qed_int_igu_init_pure_rt()
1850 		qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,  in qed_int_igu_init_pure_rt()
1856 int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)  in qed_int_igu_reset_cam()  argument
1969 		rval = qed_rd(p_hwfn, p_ptt,  in qed_int_igu_reset_cam()
1973 			qed_wr(p_hwfn, p_ptt,  in qed_int_igu_reset_cam()
1991 				       struct qed_ptt *p_ptt, u16 igu_sb_id)  in qed_int_igu_read_cam_block()  argument
1993 	u32 val = qed_rd(p_hwfn, p_ptt,  in qed_int_igu_read_cam_block()
2006 int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)  in qed_int_igu_read_cam()  argument
2033 		qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);  in qed_int_igu_read_cam()
2150 int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)  in qed_int_alloc()  argument
2158 	rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);  in qed_int_alloc()
2162 	rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);  in qed_int_alloc()
2174 void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)  in qed_int_setup()  argument
2176 	qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);  in qed_int_setup()
2177 	qed_int_sb_attn_setup(p_hwfn, p_ptt);  in qed_int_setup()
2200 int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,  in qed_int_set_timer_res()  argument
2211 	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +  in qed_int_set_timer_res()
2224 	rc = qed_dmae_host2grc(p_hwfn, p_ptt,  in qed_int_set_timer_res()