Lines Matching refs:ATTENTION_SINGLE
85 #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) macro
86 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
403 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
404 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
405 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
406 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
420 {"PGLUE config_space", ATTENTION_SINGLE,
422 {"PGLUE misc_flr", ATTENTION_SINGLE,
426 {"PGLUE misc_mctp", ATTENTION_SINGLE,
428 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
429 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
430 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
448 {"General Attention 32", ATTENTION_SINGLE,
453 {"General Attention 35", ATTENTION_SINGLE,
460 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
468 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
471 {"MCP CPU", ATTENTION_SINGLE,
473 {"MCP Watchdog timer", ATTENTION_SINGLE,
475 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
476 {"AVS stop status ready", ATTENTION_SINGLE,
551 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
581 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
583 {"PERST_B assertion", ATTENTION_SINGLE,
585 {"PERST_B deassertion", ATTENTION_SINGLE,
596 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,