Lines Matching refs:dev
68 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) in mei_me_mecbrw_read() argument
70 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); in mei_me_mecbrw_read()
79 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) in mei_me_hcbww_write() argument
81 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); in mei_me_hcbww_write()
91 static inline u32 mei_me_mecsr_read(const struct mei_device *dev) in mei_me_mecsr_read() argument
95 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); in mei_me_mecsr_read()
96 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); in mei_me_mecsr_read()
108 static inline u32 mei_hcsr_read(const struct mei_device *dev) in mei_hcsr_read() argument
112 reg = mei_me_reg_read(to_me_hw(dev), H_CSR); in mei_hcsr_read()
113 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_read()
124 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) in mei_hcsr_write() argument
126 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); in mei_hcsr_write()
127 mei_me_reg_write(to_me_hw(dev), H_CSR, reg); in mei_hcsr_write()
137 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) in mei_hcsr_set() argument
140 mei_hcsr_write(dev, reg); in mei_hcsr_set()
148 static inline void mei_hcsr_set_hig(struct mei_device *dev) in mei_hcsr_set_hig() argument
152 hcsr = mei_hcsr_read(dev) | H_IG; in mei_hcsr_set_hig()
153 mei_hcsr_set(dev, hcsr); in mei_hcsr_set_hig()
163 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) in mei_me_d0i3c_read() argument
167 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); in mei_me_d0i3c_read()
168 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_read()
179 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) in mei_me_d0i3c_write() argument
181 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); in mei_me_d0i3c_write()
182 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); in mei_me_d0i3c_write()
193 static int mei_me_fw_status(struct mei_device *dev, in mei_me_fw_status() argument
196 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_fw_status()
197 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_fw_status()
209 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", in mei_me_fw_status()
224 static void mei_me_hw_config(struct mei_device *dev) in mei_me_hw_config() argument
226 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_hw_config()
227 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_config()
231 hcsr = mei_hcsr_read(dev); in mei_me_hw_config()
236 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_hw_config()
242 reg = mei_me_d0i3c_read(dev); in mei_me_hw_config()
256 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) in mei_me_pg_state() argument
258 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_state()
275 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr) in me_intr_disable() argument
278 mei_hcsr_set(dev, hcsr); in me_intr_disable()
287 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr) in me_intr_clear() argument
290 mei_hcsr_write(dev, hcsr); in me_intr_clear()
298 static void mei_me_intr_clear(struct mei_device *dev) in mei_me_intr_clear() argument
300 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_clear()
302 me_intr_clear(dev, hcsr); in mei_me_intr_clear()
309 static void mei_me_intr_enable(struct mei_device *dev) in mei_me_intr_enable() argument
311 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_enable()
314 mei_hcsr_set(dev, hcsr); in mei_me_intr_enable()
322 static void mei_me_intr_disable(struct mei_device *dev) in mei_me_intr_disable() argument
324 u32 hcsr = mei_hcsr_read(dev); in mei_me_intr_disable()
326 me_intr_disable(dev, hcsr); in mei_me_intr_disable()
334 static void mei_me_synchronize_irq(struct mei_device *dev) in mei_me_synchronize_irq() argument
336 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_me_synchronize_irq()
346 static void mei_me_hw_reset_release(struct mei_device *dev) in mei_me_hw_reset_release() argument
348 u32 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset_release()
352 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset_release()
363 static void mei_me_host_set_ready(struct mei_device *dev) in mei_me_host_set_ready() argument
365 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_set_ready()
368 mei_hcsr_set(dev, hcsr); in mei_me_host_set_ready()
377 static bool mei_me_host_is_ready(struct mei_device *dev) in mei_me_host_is_ready() argument
379 u32 hcsr = mei_hcsr_read(dev); in mei_me_host_is_ready()
390 static bool mei_me_hw_is_ready(struct mei_device *dev) in mei_me_hw_is_ready() argument
392 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_ready()
403 static bool mei_me_hw_is_resetting(struct mei_device *dev) in mei_me_hw_is_resetting() argument
405 u32 mecsr = mei_me_mecsr_read(dev); in mei_me_hw_is_resetting()
417 static int mei_me_hw_ready_wait(struct mei_device *dev) in mei_me_hw_ready_wait() argument
419 mutex_unlock(&dev->device_lock); in mei_me_hw_ready_wait()
420 wait_event_timeout(dev->wait_hw_ready, in mei_me_hw_ready_wait()
421 dev->recvd_hw_ready, in mei_me_hw_ready_wait()
423 mutex_lock(&dev->device_lock); in mei_me_hw_ready_wait()
424 if (!dev->recvd_hw_ready) { in mei_me_hw_ready_wait()
425 dev_err(dev->dev, "wait hw ready failed\n"); in mei_me_hw_ready_wait()
429 mei_me_hw_reset_release(dev); in mei_me_hw_ready_wait()
430 dev->recvd_hw_ready = false; in mei_me_hw_ready_wait()
440 static int mei_me_hw_start(struct mei_device *dev) in mei_me_hw_start() argument
442 int ret = mei_me_hw_ready_wait(dev); in mei_me_hw_start()
446 dev_dbg(dev->dev, "hw is ready\n"); in mei_me_hw_start()
448 mei_me_host_set_ready(dev); in mei_me_hw_start()
460 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) in mei_hbuf_filled_slots() argument
465 hcsr = mei_hcsr_read(dev); in mei_hbuf_filled_slots()
480 static bool mei_me_hbuf_is_empty(struct mei_device *dev) in mei_me_hbuf_is_empty() argument
482 return mei_hbuf_filled_slots(dev) == 0; in mei_me_hbuf_is_empty()
492 static int mei_me_hbuf_empty_slots(struct mei_device *dev) in mei_me_hbuf_empty_slots() argument
494 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_empty_slots()
497 filled_slots = mei_hbuf_filled_slots(dev); in mei_me_hbuf_empty_slots()
514 static u32 mei_me_hbuf_depth(const struct mei_device *dev) in mei_me_hbuf_depth() argument
516 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hbuf_depth()
532 static int mei_me_hbuf_write(struct mei_device *dev, in mei_me_hbuf_write() argument
545 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_me_hbuf_write()
547 empty_slots = mei_hbuf_empty_slots(dev); in mei_me_hbuf_write()
548 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); in mei_me_hbuf_write()
559 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
563 mei_me_hcbww_write(dev, reg_buf[i]); in mei_me_hbuf_write()
570 mei_me_hcbww_write(dev, reg); in mei_me_hbuf_write()
573 mei_hcsr_set_hig(dev); in mei_me_hbuf_write()
574 if (!mei_me_hw_is_ready(dev)) in mei_me_hbuf_write()
587 static int mei_me_count_full_read_slots(struct mei_device *dev) in mei_me_count_full_read_slots() argument
593 me_csr = mei_me_mecsr_read(dev); in mei_me_count_full_read_slots()
603 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); in mei_me_count_full_read_slots()
616 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, in mei_me_read_slots() argument
622 *reg_buf++ = mei_me_mecbrw_read(dev); in mei_me_read_slots()
625 u32 reg = mei_me_mecbrw_read(dev); in mei_me_read_slots()
630 mei_hcsr_set_hig(dev); in mei_me_read_slots()
639 static void mei_me_pg_set(struct mei_device *dev) in mei_me_pg_set() argument
641 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_set()
645 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
649 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_set()
658 static void mei_me_pg_unset(struct mei_device *dev) in mei_me_pg_unset() argument
660 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_unset()
664 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
670 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); in mei_me_pg_unset()
681 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) in mei_me_pg_legacy_enter_sync() argument
683 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_enter_sync()
687 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_enter_sync()
689 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_pg_legacy_enter_sync()
693 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
694 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_enter_sync()
695 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_enter_sync()
696 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_enter_sync()
698 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_enter_sync()
699 mei_me_pg_set(dev); in mei_me_pg_legacy_enter_sync()
705 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_enter_sync()
718 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) in mei_me_pg_legacy_exit_sync() argument
720 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_exit_sync()
724 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) in mei_me_pg_legacy_exit_sync()
727 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_pg_legacy_exit_sync()
729 mei_me_pg_unset(dev); in mei_me_pg_legacy_exit_sync()
731 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
732 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
733 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
734 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
737 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_pg_legacy_exit_sync()
742 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_legacy_exit_sync()
743 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); in mei_me_pg_legacy_exit_sync()
747 mutex_unlock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
748 wait_event_timeout(dev->wait_pg, in mei_me_pg_legacy_exit_sync()
749 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_pg_legacy_exit_sync()
750 mutex_lock(&dev->device_lock); in mei_me_pg_legacy_exit_sync()
752 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) in mei_me_pg_legacy_exit_sync()
758 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_pg_legacy_exit_sync()
771 static bool mei_me_pg_in_transition(struct mei_device *dev) in mei_me_pg_in_transition() argument
773 return dev->pg_event >= MEI_PG_EVENT_WAIT && in mei_me_pg_in_transition()
774 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; in mei_me_pg_in_transition()
784 static bool mei_me_pg_is_enabled(struct mei_device *dev) in mei_me_pg_is_enabled() argument
786 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_is_enabled()
787 u32 reg = mei_me_mecsr_read(dev); in mei_me_pg_is_enabled()
795 if (!dev->hbm_f_pg_supported) in mei_me_pg_is_enabled()
801 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", in mei_me_pg_is_enabled()
804 dev->version.major_version, in mei_me_pg_is_enabled()
805 dev->version.minor_version, in mei_me_pg_is_enabled()
820 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) in mei_me_d0i3_set() argument
822 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
829 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_set()
831 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_set()
842 static u32 mei_me_d0i3_unset(struct mei_device *dev) in mei_me_d0i3_unset() argument
844 u32 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
848 mei_me_d0i3c_write(dev, reg); in mei_me_d0i3_unset()
850 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_unset()
861 static int mei_me_d0i3_enter_sync(struct mei_device *dev) in mei_me_d0i3_enter_sync() argument
863 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter_sync()
869 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
872 dev_dbg(dev->dev, "d0i3 set not needed\n"); in mei_me_d0i3_enter_sync()
878 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_me_d0i3_enter_sync()
880 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); in mei_me_d0i3_enter_sync()
885 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
886 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
887 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout); in mei_me_d0i3_enter_sync()
888 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
890 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_d0i3_enter_sync()
896 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_enter_sync()
898 reg = mei_me_d0i3_set(dev, true); in mei_me_d0i3_enter_sync()
900 dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); in mei_me_d0i3_enter_sync()
905 mutex_unlock(&dev->device_lock); in mei_me_d0i3_enter_sync()
906 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_enter_sync()
907 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); in mei_me_d0i3_enter_sync()
908 mutex_lock(&dev->device_lock); in mei_me_d0i3_enter_sync()
910 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_enter_sync()
911 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter_sync()
922 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter_sync()
923 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); in mei_me_d0i3_enter_sync()
937 static int mei_me_d0i3_enter(struct mei_device *dev) in mei_me_d0i3_enter() argument
939 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_enter()
942 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_enter()
945 dev_dbg(dev->dev, "already d0i3 : set not needed\n"); in mei_me_d0i3_enter()
949 mei_me_d0i3_set(dev, false); in mei_me_d0i3_enter()
952 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_enter()
953 dev_dbg(dev->dev, "d0i3 enter\n"); in mei_me_d0i3_enter()
964 static int mei_me_d0i3_exit_sync(struct mei_device *dev) in mei_me_d0i3_exit_sync() argument
966 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_exit_sync()
971 dev->pg_event = MEI_PG_EVENT_INTR_WAIT; in mei_me_d0i3_exit_sync()
973 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
976 dev_dbg(dev->dev, "d0i3 exit not needed\n"); in mei_me_d0i3_exit_sync()
981 reg = mei_me_d0i3_unset(dev); in mei_me_d0i3_exit_sync()
983 dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); in mei_me_d0i3_exit_sync()
988 mutex_unlock(&dev->device_lock); in mei_me_d0i3_exit_sync()
989 wait_event_timeout(dev->wait_pg, in mei_me_d0i3_exit_sync()
990 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); in mei_me_d0i3_exit_sync()
991 mutex_lock(&dev->device_lock); in mei_me_d0i3_exit_sync()
993 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { in mei_me_d0i3_exit_sync()
994 reg = mei_me_d0i3c_read(dev); in mei_me_d0i3_exit_sync()
1005 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_me_d0i3_exit_sync()
1007 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); in mei_me_d0i3_exit_sync()
1017 static void mei_me_pg_legacy_intr(struct mei_device *dev) in mei_me_pg_legacy_intr() argument
1019 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_legacy_intr()
1021 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) in mei_me_pg_legacy_intr()
1024 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_pg_legacy_intr()
1026 if (waitqueue_active(&dev->wait_pg)) in mei_me_pg_legacy_intr()
1027 wake_up(&dev->wait_pg); in mei_me_pg_legacy_intr()
1036 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source) in mei_me_d0i3_intr() argument
1038 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_d0i3_intr()
1040 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && in mei_me_d0i3_intr()
1042 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; in mei_me_d0i3_intr()
1045 if (dev->hbm_state != MEI_HBM_IDLE) { in mei_me_d0i3_intr()
1050 dev_dbg(dev->dev, "d0i3 set host ready\n"); in mei_me_d0i3_intr()
1051 mei_me_host_set_ready(dev); in mei_me_d0i3_intr()
1057 wake_up(&dev->wait_pg); in mei_me_d0i3_intr()
1066 dev_dbg(dev->dev, "d0i3 want resume\n"); in mei_me_d0i3_intr()
1067 mei_hbm_pg_resume(dev); in mei_me_d0i3_intr()
1077 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source) in mei_me_pg_intr() argument
1079 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_intr()
1082 mei_me_d0i3_intr(dev, intr_source); in mei_me_pg_intr()
1084 mei_me_pg_legacy_intr(dev); in mei_me_pg_intr()
1094 int mei_me_pg_enter_sync(struct mei_device *dev) in mei_me_pg_enter_sync() argument
1096 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_enter_sync()
1099 return mei_me_d0i3_enter_sync(dev); in mei_me_pg_enter_sync()
1101 return mei_me_pg_legacy_enter_sync(dev); in mei_me_pg_enter_sync()
1111 int mei_me_pg_exit_sync(struct mei_device *dev) in mei_me_pg_exit_sync() argument
1113 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_pg_exit_sync()
1116 return mei_me_d0i3_exit_sync(dev); in mei_me_pg_exit_sync()
1118 return mei_me_pg_legacy_exit_sync(dev); in mei_me_pg_exit_sync()
1129 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) in mei_me_hw_reset() argument
1131 struct mei_me_hw *hw = to_me_hw(dev); in mei_me_hw_reset()
1136 mei_me_intr_enable(dev); in mei_me_hw_reset()
1138 ret = mei_me_d0i3_exit_sync(dev); in mei_me_hw_reset()
1144 pm_runtime_set_active(dev->dev); in mei_me_hw_reset()
1146 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1153 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); in mei_me_hw_reset()
1155 mei_hcsr_set(dev, hcsr); in mei_me_hw_reset()
1156 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1164 dev->recvd_hw_ready = false; in mei_me_hw_reset()
1165 mei_hcsr_write(dev, hcsr); in mei_me_hw_reset()
1171 hcsr = mei_hcsr_read(dev); in mei_me_hw_reset()
1174 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); in mei_me_hw_reset()
1177 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); in mei_me_hw_reset()
1180 mei_me_hw_reset_release(dev); in mei_me_hw_reset()
1182 ret = mei_me_d0i3_enter(dev); in mei_me_hw_reset()
1200 struct mei_device *dev = (struct mei_device *)dev_id; in mei_me_irq_quick_handler() local
1203 hcsr = mei_hcsr_read(dev); in mei_me_irq_quick_handler()
1207 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr)); in mei_me_irq_quick_handler()
1210 me_intr_disable(dev, hcsr); in mei_me_irq_quick_handler()
1226 struct mei_device *dev = (struct mei_device *) dev_id; in mei_me_irq_thread_handler() local
1232 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); in mei_me_irq_thread_handler()
1234 mutex_lock(&dev->device_lock); in mei_me_irq_thread_handler()
1236 hcsr = mei_hcsr_read(dev); in mei_me_irq_thread_handler()
1237 me_intr_clear(dev, hcsr); in mei_me_irq_thread_handler()
1242 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { in mei_me_irq_thread_handler()
1243 dev_warn(dev->dev, "FW not ready: resetting.\n"); in mei_me_irq_thread_handler()
1244 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1248 if (mei_me_hw_is_resetting(dev)) in mei_me_irq_thread_handler()
1249 mei_hcsr_set_hig(dev); in mei_me_irq_thread_handler()
1251 mei_me_pg_intr(dev, me_intr_src(hcsr)); in mei_me_irq_thread_handler()
1254 if (!mei_host_is_ready(dev)) { in mei_me_irq_thread_handler()
1255 if (mei_hw_is_ready(dev)) { in mei_me_irq_thread_handler()
1256 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_me_irq_thread_handler()
1257 dev->recvd_hw_ready = true; in mei_me_irq_thread_handler()
1258 wake_up(&dev->wait_hw_ready); in mei_me_irq_thread_handler()
1260 dev_dbg(dev->dev, "Spurious Interrupt\n"); in mei_me_irq_thread_handler()
1265 slots = mei_count_full_read_slots(dev); in mei_me_irq_thread_handler()
1267 dev_dbg(dev->dev, "slots to read = %08x\n", slots); in mei_me_irq_thread_handler()
1268 rets = mei_irq_read_handler(dev, &cmpl_list, &slots); in mei_me_irq_thread_handler()
1277 (dev->dev_state != MEI_DEV_RESETTING && in mei_me_irq_thread_handler()
1278 dev->dev_state != MEI_DEV_POWER_DOWN)) { in mei_me_irq_thread_handler()
1279 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", in mei_me_irq_thread_handler()
1281 schedule_work(&dev->reset_work); in mei_me_irq_thread_handler()
1286 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1293 if (dev->pg_event != MEI_PG_EVENT_WAIT && in mei_me_irq_thread_handler()
1294 dev->pg_event != MEI_PG_EVENT_RECEIVED) { in mei_me_irq_thread_handler()
1295 rets = mei_irq_write_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1296 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_me_irq_thread_handler()
1299 mei_irq_compl_handler(dev, &cmpl_list); in mei_me_irq_thread_handler()
1302 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_me_irq_thread_handler()
1303 mei_me_intr_enable(dev); in mei_me_irq_thread_handler()
1304 mutex_unlock(&dev->device_lock); in mei_me_irq_thread_handler()
1344 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); in mei_me_fw_type_nm()
1363 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); in mei_me_fw_type_sps()
1472 struct mei_device *dev; in mei_me_dev_init() local
1475 dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) + in mei_me_dev_init()
1477 if (!dev) in mei_me_dev_init()
1479 hw = to_me_hw(dev); in mei_me_dev_init()
1481 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); in mei_me_dev_init()
1483 return dev; in mei_me_dev_init()