101 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)  in asic3_read_register()  function
106 EXPORT_SYMBOL_GPL(asic3_read_register);
114 	val = asic3_read_register(asic, reg);  in asic3_set_register()
135 	edge = asic3_read_register(asic,  in asic3_irq_flip_edge()
157 		status = asic3_read_register(asic,  in asic3_irq_demux()
173 				istat = asic3_read_register(asic,  in asic3_irq_demux()
236 	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);  in asic3_mask_gpio_irq()
249 	regval = asic3_read_register(asic,  in asic3_mask_irq()
273 	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);  in asic3_unmask_gpio_irq()
286 	regval = asic3_read_register(asic,  in asic3_unmask_irq()
312 	level = asic3_read_register(asic,  in asic3_gpio_irq_type()
314 	edge = asic3_read_register(asic,  in asic3_gpio_irq_type()
316 	trigger = asic3_read_register(asic,  in asic3_gpio_irq_type()
462 	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);  in asic3_gpio_direction()
506 	return !!(asic3_read_register(asic,  in asic3_gpio_get()
531 	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);  in asic3_gpio_set()
618 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_enable()
634 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_disable()