158 					     ASIC3_OFFSET(INTR, P_INT_STAT));  in asic3_irq_demux()
402 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),  in asic3_irq_probe()
418 	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),  in asic3_irq_probe()
618 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_enable()
620 		asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);  in asic3_clk_enable()
634 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_disable()
636 		asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);  in asic3_clk_disable()
671 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),  in ds1wm_enable()
674 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),  in ds1wm_enable()
677 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in ds1wm_enable()
688 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in ds1wm_disable()
747 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
749 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
751 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
753 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
764 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),  in asic3_mmc_enable()
771 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_mmc_enable()
775 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
790 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_disable()
896 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_mfd_probe()
991 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);  in asic3_probe()
1023 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_probe()
1044 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_remove()
1054 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);  in asic3_remove()