Lines Matching refs:dc
38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
43 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
86 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
109 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
305 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
310 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
320 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
325 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
328 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
338 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
408 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
511 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
602 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_atomic_check() local
621 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
632 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
753 struct tegra_dc *dc) in tegra_primary_plane_create() argument
770 plane->dc = dc; in tegra_primary_plane_create()
772 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
773 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
774 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
792 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
836 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_cursor_atomic_update() local
868 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
872 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
876 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
878 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
880 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
887 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
891 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
897 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
904 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
918 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
938 plane->dc = dc; in tegra_dc_cursor_plane_create()
1034 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1051 plane->dc = dc; in tegra_dc_overlay_plane_create()
1053 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1054 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1077 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1084 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1089 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1090 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1092 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1096 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1118 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1125 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1129 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1135 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1421 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1425 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1427 if (!dc->base.state->active) { in tegra_dc_show_regs()
1436 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1440 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1447 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1451 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1453 if (!dc->base.state->active) { in tegra_dc_show_crc()
1459 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1460 tegra_dc_commit(dc); in tegra_dc_show_crc()
1462 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1463 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1465 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1468 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1471 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1478 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1480 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1481 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1482 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1483 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1499 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1508 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1510 if (!dc->debugfs_files) in tegra_dc_late_register()
1514 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1516 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1523 kfree(dc->debugfs_files); in tegra_dc_late_register()
1524 dc->debugfs_files = NULL; in tegra_dc_late_register()
1533 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1535 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1536 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1537 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1542 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1545 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1546 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1549 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1554 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1557 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1559 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1566 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1569 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1571 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1588 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1595 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1596 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1599 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1604 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1608 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1612 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1615 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1632 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1639 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1649 static void tegra_dc_commit_state(struct tegra_dc *dc, in tegra_dc_commit_state() argument
1655 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1657 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1670 dev_err(dc->dev, in tegra_dc_commit_state()
1675 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1679 if (!dc->soc->has_nvdisplay) { in tegra_dc_commit_state()
1681 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1684 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_commit_state()
1686 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_commit_state()
1687 dc->clk, state->pclk, err); in tegra_dc_commit_state()
1690 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1695 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1697 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1699 tegra_dc_commit(dc); in tegra_dc_stop()
1702 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1706 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1711 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1716 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1722 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1729 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
1732 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
1733 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
1739 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
1758 if (dc->rgb) { in tegra_crtc_atomic_disable()
1759 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1762 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1765 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
1777 pm_runtime_put_sync(dc->dev); in tegra_crtc_atomic_disable()
1785 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
1788 pm_runtime_get_sync(dc->dev); in tegra_crtc_atomic_enable()
1791 if (dc->syncpt) { in tegra_crtc_atomic_enable()
1792 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
1794 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
1800 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
1803 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
1806 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1809 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
1816 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
1820 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
1823 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
1825 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
1829 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
1833 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
1838 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
1842 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
1846 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
1850 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
1853 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
1854 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
1856 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
1859 tegra_dc_commit_state(dc, state); in tegra_crtc_atomic_enable()
1862 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
1865 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
1866 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
1868 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
1871 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
1874 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
1876 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1877 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
1880 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
1884 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1886 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
1889 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
1917 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
1921 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1922 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1925 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1926 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1938 struct tegra_dc *dc = data; in tegra_dc_irq() local
1941 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
1942 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
1948 dc->stats.frames++; in tegra_dc_irq()
1955 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
1956 dc->stats.vblank++; in tegra_dc_irq()
1963 dc->stats.underflow++; in tegra_dc_irq()
1970 dc->stats.overflow++; in tegra_dc_irq()
1974 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
1975 dc->stats.underflow++; in tegra_dc_irq()
1985 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
1991 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
1992 if (!dc->syncpt) in tegra_dc_init()
1993 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
1995 dc->group = host1x_client_iommu_attach(client, true); in tegra_dc_init()
1996 if (IS_ERR(dc->group)) { in tegra_dc_init()
1997 err = PTR_ERR(dc->group); in tegra_dc_init()
2002 if (dc->soc->wgrps) in tegra_dc_init()
2003 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2005 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2012 if (dc->soc->supports_cursor) { in tegra_dc_init()
2013 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2020 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2027 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2032 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2038 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2039 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2041 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2043 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2047 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2048 dev_name(dc->dev), dc); in tegra_dc_init()
2050 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2064 host1x_client_iommu_detach(client, dc->group); in tegra_dc_init()
2065 host1x_syncpt_free(dc->syncpt); in tegra_dc_init()
2072 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2075 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2077 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2079 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2083 host1x_client_iommu_detach(client, dc->group); in tegra_dc_exit()
2084 host1x_syncpt_free(dc->syncpt); in tegra_dc_exit()
2192 .dc = 0,
2197 .dc = 1,
2202 .dc = 1,
2207 .dc = 2,
2212 .dc = 2,
2217 .dc = 2,
2262 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
2268 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
2270 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
2285 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
2294 dc->pipe = value; in tegra_dc_parse_dt()
2301 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
2304 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
2307 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
2314 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
2319 partner = driver_find_device(dc->dev->driver, NULL, NULL, in tegra_dc_couple()
2324 link = device_link_add(dc->dev, partner, flags); in tegra_dc_couple()
2326 dev_err(dc->dev, "failed to link controllers\n"); in tegra_dc_couple()
2330 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner)); in tegra_dc_couple()
2339 struct tegra_dc *dc; in tegra_dc_probe() local
2342 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
2343 if (!dc) in tegra_dc_probe()
2346 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
2348 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
2349 dc->dev = &pdev->dev; in tegra_dc_probe()
2351 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
2355 err = tegra_dc_couple(dc); in tegra_dc_probe()
2359 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
2360 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
2362 return PTR_ERR(dc->clk); in tegra_dc_probe()
2365 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
2366 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
2368 return PTR_ERR(dc->rst); in tegra_dc_probe()
2372 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
2378 err = reset_control_assert(dc->rst); in tegra_dc_probe()
2384 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
2386 if (dc->soc->has_powergate) { in tegra_dc_probe()
2387 if (dc->pipe == 0) in tegra_dc_probe()
2388 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
2390 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
2392 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
2396 dc->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dc_probe()
2397 if (IS_ERR(dc->regs)) in tegra_dc_probe()
2398 return PTR_ERR(dc->regs); in tegra_dc_probe()
2400 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
2401 if (dc->irq < 0) { in tegra_dc_probe()
2406 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
2412 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
2415 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
2416 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
2417 dc->client.dev = &pdev->dev; in tegra_dc_probe()
2419 err = host1x_client_register(&dc->client); in tegra_dc_probe()
2431 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
2434 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
2441 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()
2455 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_suspend() local
2458 err = reset_control_assert(dc->rst); in tegra_dc_suspend()
2464 if (dc->soc->has_powergate) in tegra_dc_suspend()
2465 tegra_powergate_power_off(dc->powergate); in tegra_dc_suspend()
2467 clk_disable_unprepare(dc->clk); in tegra_dc_suspend()
2474 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_resume() local
2477 if (dc->soc->has_powergate) { in tegra_dc_resume()
2478 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_resume()
2479 dc->rst); in tegra_dc_resume()
2485 err = clk_prepare_enable(dc->clk); in tegra_dc_resume()
2491 err = reset_control_deassert(dc->rst); in tegra_dc_resume()