Lines Matching refs:apbc_base

75 	void __iomem *apbc_base;  in pxa168_clk_init()  local
89 apbc_base = ioremap(apbc_phys, SZ_4K); in pxa168_clk_init()
90 if (!apbc_base) { in pxa168_clk_init()
164 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa168_clk_init()
168 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); in pxa168_clk_init()
172 apbc_base + APBC_GPIO, 10, 0, &clk_lock); in pxa168_clk_init()
176 apbc_base + APBC_KPC, 10, 0, &clk_lock); in pxa168_clk_init()
180 apbc_base + APBC_RTC, 10, 0, &clk_lock); in pxa168_clk_init()
184 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
188 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa168_clk_init()
192 apbc_base + APBC_PWM2, 10, 0, &clk_lock); in pxa168_clk_init()
196 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa168_clk_init()
202 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
207 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa168_clk_init()
213 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
218 apbc_base + APBC_UART1, 10, 0, &clk_lock); in pxa168_clk_init()
224 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
229 apbc_base + APBC_UART2, 10, 0, &clk_lock); in pxa168_clk_init()
235 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
238 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, in pxa168_clk_init()
245 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
248 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, in pxa168_clk_init()
255 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
258 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, in pxa168_clk_init()
265 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); in pxa168_clk_init()
268 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, in pxa168_clk_init()
275 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); in pxa168_clk_init()
278 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, in pxa168_clk_init()