Lines Matching refs:pm07_cntrl
130 u32 pm07_cntrl[NR_PHYS_CTRS]; member
295 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES; in set_pm_event()
303 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
319 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
320 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles); in set_pm_event()
321 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity); in set_pm_event()
322 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control); in set_pm_event()
347 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit); in set_pm_event()
349 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
428 static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl) in enable_ctr() argument
431 pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE; in enable_ctr()
432 cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]); in enable_ctr()
539 pm_regs.pm07_cntrl); in cell_virtual_cntr()
664 enable_ctr(cpu, 0, pm_regs.pm07_cntrl); in spu_evnt_swap()
1370 enable_ctr(cpu, 0, pm_regs.pm07_cntrl); in cell_global_start_spu_events()
1416 enable_ctr(cpu, i, pm_regs.pm07_cntrl); in cell_global_start_ppu()