63 #define IS_LE	1  macro
66 #define IS_LE	0  macro
626 		err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);  in emulate_lq()
652 	err = write_mem(vals[IS_LE], ea, 8, regs);  in emulate_stq()
678 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_load()
686 		i = IS_LE ? 8 : 8 - read_size;  in emulate_vsx_load()
693 				reg->d[IS_LE] = (signed int) reg->d[IS_LE];  in emulate_vsx_load()
696 				conv_sp_to_dp(&reg->fp[1 + IS_LE],  in emulate_vsx_load()
697 					      &reg->dp[IS_LE]);  in emulate_vsx_load()
705 				reg->d[IS_BE] = reg->d[IS_LE];  in emulate_vsx_load()
712 			i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
716 			u32 val = reg->w[IS_LE ? 3 : 0];  in emulate_vsx_load()
718 				i = IS_LE ? 3 - j : j;  in emulate_vsx_load()
727 			i = IS_LE ? 7 - j : j;  in emulate_vsx_load()
735 			i = IS_LE ? 15 - j : j;  in emulate_vsx_load()
761 		if (IS_LE && (op->vsx_flags & VSX_LDLEFT))  in emulate_vsx_store()
774 		i = IS_LE ? 8 : 8 - write_size;  in emulate_vsx_store()
778 			conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);  in emulate_vsx_store()
795 			i = IS_LE ? 3 - j : j;  in emulate_vsx_store()
803 			i = IS_LE ? 7 - j : j;  in emulate_vsx_store()
811 			i = IS_LE ? 15 - j : j;  in emulate_vsx_store()