Lines Matching refs:IPC
32 | EHCI/XHCI | --> | ISH IPC |
85 | IPC Drivers |
103 3.2 Inter Processor Communication (IPC) driver
106 The IPC message used memory mapped I/O. The registers are defined in
109 3.2.1 IPC/FW message types
117 RX (E.g.IPC_REG_ISH2HOST_MSG, IPC_REG_HOST2ISH_MSG). The IPC layer maintains
129 Bits 16..19: management command (for IPC management protocol)
135 To abstract HW level IPC communication, a set of callbacks are registered.
175 whether to send over IPC or over DMA; for each transfer the decision is
198 (up to IPC MTU), thus allowing for interrupt throttling.
199 Currently, ISH FW decides to send over DMA if ISHTP message is more than 3 IPC
200 fragments and via IPC otherwise.
253 HID-ISH-CLN ISHTP IPC HW