1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33 /* *INDENT-OFF* */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 /* *INDENT-ON* */
38
39 /*-----------------------------------------------------------
40 * Port specific definitions.
41 *
42 * The settings in this file configure FreeRTOS correctly for the
43 * given hardware and compiler.
44 *
45 * These settings should not be altered.
46 *-----------------------------------------------------------
47 */
48
49 /* Type definitions. */
50 #define portCHAR char
51 #define portFLOAT float
52 #define portDOUBLE double
53 #define portLONG long
54 #define portSHORT short
55 #define portSTACK_TYPE uint32_t
56 #define portBASE_TYPE long
57
58 typedef portSTACK_TYPE StackType_t;
59 typedef long BaseType_t;
60 typedef unsigned long UBaseType_t;
61
62 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
63 typedef uint16_t TickType_t;
64 #define portMAX_DELAY ( TickType_t ) 0xffff
65 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
66 typedef uint32_t TickType_t;
67 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
68
69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
70 * not need to be guarded with a critical section. */
71 #define portTICK_TYPE_IS_ATOMIC 1
72 #else
73 #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
74 #endif
75
76 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
77 * and r0p1 cores. */
78 #ifndef configENABLE_ERRATA_837070_WORKAROUND
79 #define configENABLE_ERRATA_837070_WORKAROUND 0
80 #endif
81 /*-----------------------------------------------------------*/
82
83 /* MPU specific constants. */
84 #define portUSING_MPU_WRAPPERS 1
85 #define portPRIVILEGE_BIT ( 0x80000000UL )
86
87 #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
88 #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
89 #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
90 #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
91 #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
92 #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
93 #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
94
95 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
96 * Register (RASR). */
97 #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
98 #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
99
100 /* MPU settings that can be overriden in FreeRTOSConfig.h. */
101 #ifndef configTOTAL_MPU_REGIONS
102 /* Define to 8 for backward compatibility. */
103 #define configTOTAL_MPU_REGIONS ( 8UL )
104 #endif
105
106 /*
107 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
108 * memory type, and where necessary the cacheable and shareable properties
109 * of the memory region.
110 *
111 * The TEX, C, and B bits together indicate the memory type of the region,
112 * and:
113 * - For Normal memory, the cacheable properties of the region.
114 * - For Device memory, whether the region is shareable.
115 *
116 * For Normal memory regions, the S bit indicates whether the region is
117 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
118 *
119 * See the following two tables for setting TEX, S, C and B bits for
120 * unprivileged flash, privileged flash and privileged RAM regions.
121 *
122 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
123 | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
124 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
125 | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
126 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
127 | 000 | 0 | 1 | Device | Shared device | Shareable |
128 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
129 | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
130 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
131 | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
132 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
133 | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
134 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
135 | 001 | 0 | 1 | Reserved | Reserved | Reserved |
136 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
137 | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
138 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
139 | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
140 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
141 | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
142 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
143 | 010 | 0 | 1 | Reserved | Reserved | Reserved |
144 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
145 | 010 | 1 | X | Reserved | Reserved | Reserved |
146 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
147 | 011 | X | X | Reserved | Reserved | Reserved |
148 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
149 | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
150 | | | | | outer cacheability rules that must be exported on the | |
151 | | | | | bus. See the table below for the cacheability policy | |
152 | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
153 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
154 |
155 +-----------------------------------------+----------------------------------------+
156 | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
157 +-----------------------------------------+----------------------------------------+
158 | 00 | Non-cacheable |
159 +-----------------------------------------+----------------------------------------+
160 | 01 | Write-back, write and read allocate |
161 +-----------------------------------------+----------------------------------------+
162 | 10 | Write-through, no write allocate |
163 +-----------------------------------------+----------------------------------------+
164 | 11 | Write-back, no write allocate |
165 +-----------------------------------------+----------------------------------------+
166 */
167
168 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash
169 * region. */
170 #ifndef configTEX_S_C_B_FLASH
171 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
172 #define configTEX_S_C_B_FLASH ( 0x07UL )
173 #endif
174
175 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM
176 * region. */
177 #ifndef configTEX_S_C_B_SRAM
178 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
179 #define configTEX_S_C_B_SRAM ( 0x07UL )
180 #endif
181
182 #define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL )
183 #define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL )
184 #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
185 #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
186 #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
187 #define portFIRST_CONFIGURABLE_REGION ( 0UL )
188 #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
189 #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
190 #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
191
192 typedef struct MPU_REGION_REGISTERS
193 {
194 uint32_t ulRegionBaseAddress;
195 uint32_t ulRegionAttribute;
196 } xMPU_REGION_REGISTERS;
197
198 typedef struct MPU_REGION_SETTINGS
199 {
200 uint32_t ulRegionStartAddress;
201 uint32_t ulRegionEndAddress;
202 uint32_t ulRegionPermissions;
203 } xMPU_REGION_SETTINGS;
204
205 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
206
207 #ifndef configSYSTEM_CALL_STACK_SIZE
208 #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
209 #endif
210
211 typedef struct SYSTEM_CALL_STACK_INFO
212 {
213 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
214 uint32_t * pulSystemCallStack;
215 uint32_t * pulTaskStack;
216 uint32_t ulLinkRegisterAtSystemCallEntry;
217 } xSYSTEM_CALL_STACK_INFO;
218
219 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
220
221 #define MAX_CONTEXT_SIZE ( 52 )
222
223 /* Size of an Access Control List (ACL) entry in bits. */
224 #define portACL_ENTRY_SIZE_BITS ( 32U )
225
226 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
227 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
228 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
229
230 typedef struct MPU_SETTINGS
231 {
232 xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
233 xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
234 uint32_t ulContext[ MAX_CONTEXT_SIZE ];
235 uint32_t ulTaskFlags;
236
237 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
238 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
239 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
240 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
241 #endif
242 #endif
243 } xMPU_SETTINGS;
244
245 /* Architecture specifics. */
246 #define portSTACK_GROWTH ( -1 )
247 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
248 #define portBYTE_ALIGNMENT 8
249
250 /* Constants used with memory barrier intrinsics. */
251 #define portSY_FULL_READ_WRITE ( 15 )
252
253 /*-----------------------------------------------------------*/
254
255 /* SVC numbers for various services. */
256 #define portSVC_START_SCHEDULER 100
257 #define portSVC_YIELD 101
258 #define portSVC_RAISE_PRIVILEGE 102
259 #define portSVC_SYSTEM_CALL_EXIT 103
260
261 /* Scheduler utilities. */
262
263 #define portYIELD() __asm { SVC portSVC_YIELD }
264 #define portYIELD_WITHIN_API() \
265 { \
266 /* Set a PendSV to request a context switch. */ \
267 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
268 \
269 /* Barriers are normally not required but do ensure the code is completely \
270 * within the specified behaviour for the architecture. */ \
271 __dsb( portSY_FULL_READ_WRITE ); \
272 __isb( portSY_FULL_READ_WRITE ); \
273 }
274 /*-----------------------------------------------------------*/
275
276 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
277 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
278 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
279 do \
280 { \
281 if( xSwitchRequired ) \
282 { \
283 traceISR_EXIT_TO_SCHEDULER(); \
284 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
285 } \
286 else \
287 { \
288 traceISR_EXIT(); \
289 } \
290 } while( 0 )
291 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
292 /*-----------------------------------------------------------*/
293
294 /* Critical section management. */
295 extern void vPortEnterCritical( void );
296 extern void vPortExitCritical( void );
297
298 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
299 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
300 #define portENTER_CRITICAL() vPortEnterCritical()
301 #define portEXIT_CRITICAL() vPortExitCritical()
302 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
303 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
304
305 /*-----------------------------------------------------------*/
306
307 /* Architecture specific optimisations. */
308 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
309 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
310 #endif
311
312 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
313
314 /* Check the configuration. */
315 #if ( configMAX_PRIORITIES > 32 )
316 #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
317 #endif
318
319 /* Store/clear the ready priorities in a bit map. */
320 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
321 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
322
323 /*-----------------------------------------------------------*/
324
325 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
326
327 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
328 /*-----------------------------------------------------------*/
329
330 /* Task function macros as described on the FreeRTOS.org WEB site. These are
331 * not necessary for to use this port. They are defined so the common demo files
332 * (which build with all the ports) will build. */
333 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
334 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
335 /*-----------------------------------------------------------*/
336
337 #ifdef configASSERT
338 void vPortValidateInterruptPriority( void );
339 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
340 #endif
341
342 /* portNOP() is not required by this port. */
343 #define portNOP()
344
345 #define portINLINE __inline
346
347 #ifndef portFORCE_INLINE
348 #define portFORCE_INLINE __forceinline
349 #endif
350 /*-----------------------------------------------------------*/
351
352 extern BaseType_t xIsPrivileged( void );
353 extern void vResetPrivilege( void );
354 extern void vPortSwitchToUserMode( void );
355
356 /**
357 * @brief Checks whether or not the processor is privileged.
358 *
359 * @return 1 if the processor is already privileged, 0 otherwise.
360 */
361 #define portIS_PRIVILEGED() xIsPrivileged()
362
363 /**
364 * @brief Raise an SVC request to raise privilege.
365 */
366 #define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
367
368 /**
369 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
370 * register.
371 */
372 #define portRESET_PRIVILEGE() vResetPrivilege()
373
374 /**
375 * @brief Make a task unprivileged.
376 *
377 * It must be called from privileged tasks only. Calling it from unprivileged
378 * task will result in a memory protection fault.
379 */
380 #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
381 /*-----------------------------------------------------------*/
382
383 extern BaseType_t xPortIsTaskPrivileged( void );
384
385 /**
386 * @brief Checks whether or not the calling task is privileged.
387 *
388 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
389 */
390 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
391 /*-----------------------------------------------------------*/
392
vPortSetBASEPRI(uint32_t ulBASEPRI)393 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
394 {
395 __asm
396 {
397 /* Barrier instructions are not used as this function is only used to
398 * lower the BASEPRI value. */
399 /* *INDENT-OFF* */
400 msr basepri, ulBASEPRI
401 /* *INDENT-ON* */
402 }
403 }
404 /*-----------------------------------------------------------*/
405
vPortRaiseBASEPRI(void)406 static portFORCE_INLINE void vPortRaiseBASEPRI( void )
407 {
408 uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
409
410 __asm
411 {
412 /* Set BASEPRI to the max syscall priority to effect a critical
413 * section. */
414 /* *INDENT-OFF* */
415 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
416 cpsid i
417 #endif
418 msr basepri, ulNewBASEPRI
419 dsb
420 isb
421 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
422 cpsie i
423 #endif
424 /* *INDENT-ON* */
425 }
426 }
427 /*-----------------------------------------------------------*/
428
vPortClearBASEPRIFromISR(void)429 static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
430 {
431 __asm
432 {
433 /* Set BASEPRI to 0 so no interrupts are masked. This function is only
434 * used to lower the mask in an interrupt, so memory barriers are not
435 * used. */
436 /* *INDENT-OFF* */
437 msr basepri, # 0
438 /* *INDENT-ON* */
439 }
440 }
441 /*-----------------------------------------------------------*/
442
ulPortRaiseBASEPRI(void)443 static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
444 {
445 uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
446
447 __asm
448 {
449 /* Set BASEPRI to the max syscall priority to effect a critical
450 * section. */
451 /* *INDENT-OFF* */
452 mrs ulReturn, basepri
453 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
454 cpsid i
455 #endif
456 msr basepri, ulNewBASEPRI
457 dsb
458 isb
459 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
460 cpsie i
461 #endif
462 /* *INDENT-ON* */
463 }
464
465 return ulReturn;
466 }
467 /*-----------------------------------------------------------*/
468
xPortIsInsideInterrupt(void)469 static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
470 {
471 uint32_t ulCurrentInterrupt;
472 BaseType_t xReturn;
473
474 /* Obtain the number of the currently executing interrupt. */
475 __asm
476 {
477 mrs ulCurrentInterrupt, ipsr
478 }
479
480 if( ulCurrentInterrupt == 0 )
481 {
482 xReturn = pdFALSE;
483 }
484 else
485 {
486 xReturn = pdTRUE;
487 }
488
489 return xReturn;
490 }
491 /*-----------------------------------------------------------*/
492
493 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
494 #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
495 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
496 #endif
497 /*-----------------------------------------------------------*/
498
499 /* *INDENT-OFF* */
500 #ifdef __cplusplus
501 }
502 #endif
503 /* *INDENT-ON* */
504
505 #endif /* PORTMACRO_H */
506