1 /* 2 * FreeRTOS Kernel V11.1.0 3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * https://www.FreeRTOS.org 25 * https://github.com/FreeRTOS 26 * 27 */ 28 #ifndef PORTHARDWARE_H 29 #define PORTHARDWARE_H 30 31 #ifndef __IAR_SYSTEMS_ASM__ 32 #include <ioavr.h> 33 #endif 34 #include "FreeRTOSConfig.h" 35 36 /*-----------------------------------------------------------*/ 37 38 #if ( configUSE_TIMER_INSTANCE == 0 ) 39 40 #define TICK_INT_vect TCB0_INT_vect 41 #define INT_FLAGS TCB0_INTFLAGS 42 #define INT_MASK TCB_CAPT_bm 43 44 #define TICK_init() \ 45 { \ 46 TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 47 TCB0.INTCTRL = TCB_CAPT_bm; \ 48 TCB0.CTRLA = TCB_ENABLE_bm; \ 49 } 50 51 #elif ( configUSE_TIMER_INSTANCE == 1 ) 52 53 #define TICK_INT_vect TCB1_INT_vect 54 #define INT_FLAGS TCB1_INTFLAGS 55 #define INT_MASK TCB_CAPT_bm 56 57 #define TICK_init() \ 58 { \ 59 TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 60 TCB1.INTCTRL = TCB_CAPT_bm; \ 61 TCB1.CTRLA = TCB_ENABLE_bm; \ 62 } 63 64 #elif ( configUSE_TIMER_INSTANCE == 2 ) 65 66 #define TICK_INT_vect TCB2_INT_vect 67 #define INT_FLAGS TCB2_INTFLAGS 68 #define INT_MASK TCB_CAPT_bm 69 70 #define TICK_init() \ 71 { \ 72 TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 73 TCB2.INTCTRL = TCB_CAPT_bm; \ 74 TCB2.CTRLA = TCB_ENABLE_bm; \ 75 } 76 77 #elif ( configUSE_TIMER_INSTANCE == 3 ) 78 79 #define TICK_INT_vect TCB3_INT_vect 80 #define INT_FLAGS TCB3_INTFLAGS 81 #define INT_MASK TCB_CAPT_bm 82 83 #define TICK_init() \ 84 { \ 85 TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 86 TCB3.INTCTRL = TCB_CAPT_bm; \ 87 TCB3.CTRLA = TCB_ENABLE_bm; \ 88 } 89 90 #elif ( configUSE_TIMER_INSTANCE == 4 ) 91 92 #define TICK_INT_vect TCB4_INT_vect 93 #define INT_FLAGS TCB4_INTFLAGS 94 #define INT_MASK TCB_CAPT_bm 95 96 #define TICK_init() \ 97 { \ 98 TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ 99 TCB4.INTCTRL = TCB_CAPT_bm; \ 100 TCB4.CTRLA = TCB_ENABLE_bm; \ 101 } 102 103 #elif ( configUSE_TIMER_INSTANCE == 5 ) 104 105 #define TICK_INT_vect RTC_CNT_vect 106 #define INT_FLAGS RTC_INTFLAGS 107 #define INT_MASK RTC_OVF_bm 108 109 /* Hertz to period for RTC setup */ 110 #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) 111 #define TICK_init() \ 112 { \ 113 while( RTC.STATUS > 0 ) {; } \ 114 RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ 115 RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ 116 RTC.INTCTRL |= 1 << RTC_OVF_bp; \ 117 } 118 119 #else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ 120 #undef TICK_INT_vect 121 #undef INT_FLAGS 122 #undef INT_MASK 123 #undef TICK_init() 124 #error Invalid timer setting. 125 #endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ 126 127 /*-----------------------------------------------------------*/ 128 129 #endif /* PORTHARDWARE_H */ 130
