1/*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT AND BSD-3-Clause
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29/*This file is prepared for Doxygen automatic documentation generation.*/
30/*! \file *********************************************************************
31 *
32 * \brief Exception and interrupt vectors.
33 *
34 * This file maps all events supported by an AVR32UC.
35 *
36 * - Compiler:           IAR EWAVR32
37 * - Supported devices:  All AVR32UC devices with an INTC module can be used.
38 * - AppNote:
39 *
40 * \author               Atmel Corporation (Now Microchip):
41                                          https://www.microchip.com \n
42 *                       Support and FAQ: https://www.microchip.com/support
43 *
44 ******************************************************************************/
45
46/*
47 * Copyright (c) 2007, Atmel Corporation All rights reserved.
48 *
49 * Redistribution and use in source and binary forms, with or without
50 * modification, are permitted provided that the following conditions are met:
51 *
52 * 1. Redistributions of source code must retain the above copyright notice,
53 * this list of conditions and the following disclaimer.
54 *
55 * 2. Redistributions in binary form must reproduce the above copyright notice,
56 * this list of conditions and the following disclaimer in the documentation
57 * and/or other materials provided with the distribution.
58 *
59 * 3. The name of ATMEL may not be used to endorse or promote products derived
60 * from this software without specific prior written permission.
61 *
62 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
63 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
64 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
65 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
66 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
67 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
68 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
69 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
70 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
71 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
72 */
73
74
75#include <avr32/io.h>
76#include "intc.h"
77
78
79//! @{
80//! \verbatim
81
82
83// Start of Exception Vector Table.
84
85  // EVBA must be aligned with a power of two strictly greater than the EVBA-
86  // relative offset of the last vector.
87  COMMON  EVTAB:CODE:ROOT(9)
88
89
90  // Force EVBA initialization.
91  EXTERN  ??init_EVBA
92  REQUIRE ??init_EVBA
93
94  // Export symbol.
95  PUBLIC  ??EVBA
96  PUBLIC  _evba
97??EVBA:
98_evba:
99
100        ORG 0x000
101        // Unrecoverable Exception.
102_handle_Unrecoverable_Exception:
103        rjmp $
104
105        ORG 0x004
106        // TLB Multiple Hit: UNUSED IN AVR32UC.
107_handle_TLB_Multiple_Hit:
108        rjmp $
109
110        ORG 0x008
111        // Bus Error Data Fetch.
112_handle_Bus_Error_Data_Fetch:
113        rjmp $
114
115        ORG 0x00C
116         // Bus Error Instruction Fetch.
117_handle_Bus_Error_Instruction_Fetch:
118        rjmp $
119
120        ORG 0x010
121        // NMI.
122_handle_NMI:
123        rjmp $
124
125        ORG 0x014
126        // Instruction Address.
127_handle_Instruction_Address:
128        rjmp $
129
130        ORG 0x018
131        // ITLB Protection.
132_handle_ITLB_Protection:
133        rjmp $
134
135        ORG 0x01C
136        // Breakpoint.
137_handle_Breakpoint:
138        rjmp $
139
140        ORG 0x020
141        // Illegal Opcode.
142_handle_Illegal_Opcode:
143        rjmp $
144
145        ORG 0x024
146        // Unimplemented Instruction.
147_handle_Unimplemented_Instruction:
148        rjmp $
149
150        ORG 0x028
151        // Privilege Violation.
152_handle_Privilege_Violation:
153        rjmp $
154
155        ORG 0x02C
156        // Floating-Point: UNUSED IN AVR32UC.
157_handle_Floating_Point:
158        rjmp $
159
160        ORG 0x030
161        // Coprocessor Absent: UNUSED IN AVR32UC.
162_handle_Coprocessor_Absent:
163        rjmp $
164
165        ORG 0x034
166        // Data Address (Read).
167_handle_Data_Address_Read:
168        rjmp $
169
170        ORG 0x038
171        // Data Address (Write).
172_handle_Data_Address_Write:
173        rjmp $
174
175        ORG 0x03C
176        // DTLB Protection (Read).
177_handle_DTLB_Protection_Read:
178        rjmp $
179
180        ORG 0x040
181        // DTLB Protection (Write).
182_handle_DTLB_Protection_Write:
183        rjmp $
184
185        ORG 0x044
186        // DTLB Modified: UNUSED IN AVR32UC.
187_handle_DTLB_Modified:
188        rjmp $
189
190        ORG 0x050
191        // ITLB Miss: UNUSED IN AVR32UC.
192_handle_ITLB_Miss:
193        rjmp $
194
195        ORG 0x060
196        // DTLB Miss (Read): UNUSED IN AVR32UC.
197_handle_DTLB_Miss_Read:
198        rjmp $
199
200        ORG 0x070
201        // DTLB Miss (Write): UNUSED IN AVR32UC.
202_handle_DTLB_Miss_Write:
203        rjmp $
204
205        ORG 0x100
206        // Supervisor Call.
207_handle_Supervisor_Call:
208        lddpc   pc, __SCALLYield
209
210
211// Interrupt support.
212// The interrupt controller must provide the offset address relative to EVBA.
213// Important note:
214//   All interrupts call a C function named _get_interrupt_handler.
215//   This function will read group and interrupt line number to then return in
216//   R12 a pointer to a user-provided interrupt handler.
217
218  ALIGN 2
219
220_int0:
221  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
222  // CPU upon interrupt entry.
223#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
224  mfsr    r12, AVR32_SR
225  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
226  cp.w    r12, 110b
227  brlo    _int0_normal
228  lddsp   r12, sp[0 * 4]
229  stdsp   sp[6 * 4], r12
230  lddsp   r12, sp[1 * 4]
231  stdsp   sp[7 * 4], r12
232  lddsp   r12, sp[3 * 4]
233  sub     sp, -6 * 4
234  rete
235_int0_normal:
236#endif
237  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
238  mcall   __get_interrupt_handler
239  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
240  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
241  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
242
243_int1:
244  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
245  // CPU upon interrupt entry.
246#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
247  mfsr    r12, AVR32_SR
248  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
249  cp.w    r12, 110b
250  brlo    _int1_normal
251  lddsp   r12, sp[0 * 4]
252  stdsp   sp[6 * 4], r12
253  lddsp   r12, sp[1 * 4]
254  stdsp   sp[7 * 4], r12
255  lddsp   r12, sp[3 * 4]
256  sub     sp, -6 * 4
257  rete
258_int1_normal:
259#endif
260  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
261  mcall   __get_interrupt_handler
262  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
263  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
264  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
265
266_int2:
267  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
268  // CPU upon interrupt entry.
269#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
270  mfsr    r12, AVR32_SR
271  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
272  cp.w    r12, 110b
273  brlo    _int2_normal
274  lddsp   r12, sp[0 * 4]
275  stdsp   sp[6 * 4], r12
276  lddsp   r12, sp[1 * 4]
277  stdsp   sp[7 * 4], r12
278  lddsp   r12, sp[3 * 4]
279  sub     sp, -6 * 4
280  rete
281_int2_normal:
282#endif
283  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
284  mcall   __get_interrupt_handler
285  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
286  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
287  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
288
289_int3:
290  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
291  // CPU upon interrupt entry.
292#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
293  mfsr    r12, AVR32_SR
294  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
295  cp.w    r12, 110b
296  brlo    _int3_normal
297  lddsp   r12, sp[0 * 4]
298  stdsp   sp[6 * 4], r12
299  lddsp   r12, sp[1 * 4]
300  stdsp   sp[7 * 4], r12
301  lddsp   r12, sp[3 * 4]
302  sub     sp, -6 * 4
303  rete
304_int3_normal:
305#endif
306  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
307  mcall   __get_interrupt_handler
308  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
309  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
310  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
311
312
313// Constant data area.
314
315  ALIGN 2
316
317  // Import symbols.
318  EXTERN  SCALLYield
319  EXTERN  _get_interrupt_handler
320__SCALLYield:
321  DC32  SCALLYield
322__get_interrupt_handler:
323  DC32  _get_interrupt_handler
324
325  // Values to store in the interrupt priority registers for the various interrupt priority levels.
326  // The interrupt priority registers contain the interrupt priority level and
327  // the EVBA-relative interrupt vector offset.
328  PUBLIC  ipr_val
329ipr_val:
330  DC32  (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
331        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
332        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
333        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
334
335
336  END
337
338
339//! \endverbatim
340//! @}
341