1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33 /* *INDENT-OFF* */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 /* *INDENT-ON* */
38
39 /*-----------------------------------------------------------
40 * Port specific definitions.
41 *
42 * The settings in this file configure FreeRTOS correctly for the
43 * given hardware and compiler.
44 *
45 * These settings should not be altered.
46 *-----------------------------------------------------------
47 */
48
49 /* IAR includes. */
50 #include <intrinsics.h>
51
52 /* Type definitions. */
53 #define portCHAR char
54 #define portFLOAT float
55 #define portDOUBLE double
56 #define portLONG long
57 #define portSHORT short
58 #define portSTACK_TYPE uint32_t
59 #define portBASE_TYPE long
60
61 typedef portSTACK_TYPE StackType_t;
62 typedef long BaseType_t;
63 typedef unsigned long UBaseType_t;
64
65 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
66 typedef uint16_t TickType_t;
67 #define portMAX_DELAY ( TickType_t ) 0xffff
68 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
69 typedef uint32_t TickType_t;
70 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
71
72 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
73 * not need to be guarded with a critical section. */
74 #define portTICK_TYPE_IS_ATOMIC 1
75 #else
76 #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
77 #endif
78
79 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
80 * and r0p1 cores. */
81 #ifndef configENABLE_ERRATA_837070_WORKAROUND
82 #define configENABLE_ERRATA_837070_WORKAROUND 0
83 #endif
84 /*-----------------------------------------------------------*/
85
86 /* MPU specific constants. */
87 #define portUSING_MPU_WRAPPERS 1
88 #define portPRIVILEGE_BIT ( 0x80000000UL )
89
90 #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
91 #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
92 #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
93 #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
94 #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
95 #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
96 #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
97
98 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
99 * Register (RASR). */
100 #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
101 #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
102
103 /* MPU settings that can be overriden in FreeRTOSConfig.h. */
104 #ifndef configTOTAL_MPU_REGIONS
105 /* Define to 8 for backward compatibility. */
106 #define configTOTAL_MPU_REGIONS ( 8UL )
107 #endif
108
109 /*
110 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
111 * memory type, and where necessary the cacheable and shareable properties
112 * of the memory region.
113 *
114 * The TEX, C, and B bits together indicate the memory type of the region,
115 * and:
116 * - For Normal memory, the cacheable properties of the region.
117 * - For Device memory, whether the region is shareable.
118 *
119 * For Normal memory regions, the S bit indicates whether the region is
120 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
121 *
122 * See the following two tables for setting TEX, S, C and B bits for
123 * unprivileged flash, privileged flash and privileged RAM regions.
124 *
125 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
126 | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
127 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
128 | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
129 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
130 | 000 | 0 | 1 | Device | Shared device | Shareable |
131 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
132 | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
133 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
134 | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
135 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
136 | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
137 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
138 | 001 | 0 | 1 | Reserved | Reserved | Reserved |
139 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
140 | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
141 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
142 | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
143 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
144 | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
145 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
146 | 010 | 0 | 1 | Reserved | Reserved | Reserved |
147 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
148 | 010 | 1 | X | Reserved | Reserved | Reserved |
149 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
150 | 011 | X | X | Reserved | Reserved | Reserved |
151 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
152 | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
153 | | | | | outer cacheability rules that must be exported on the | |
154 | | | | | bus. See the table below for the cacheability policy | |
155 | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
156 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
157 |
158 +-----------------------------------------+----------------------------------------+
159 | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
160 +-----------------------------------------+----------------------------------------+
161 | 00 | Non-cacheable |
162 +-----------------------------------------+----------------------------------------+
163 | 01 | Write-back, write and read allocate |
164 +-----------------------------------------+----------------------------------------+
165 | 10 | Write-through, no write allocate |
166 +-----------------------------------------+----------------------------------------+
167 | 11 | Write-back, no write allocate |
168 +-----------------------------------------+----------------------------------------+
169 */
170
171 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
172 * region. */
173 #ifndef configTEX_S_C_B_FLASH
174 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
175 #define configTEX_S_C_B_FLASH ( 0x07UL )
176 #endif
177
178 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
179 * region. */
180 #ifndef configTEX_S_C_B_SRAM
181 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
182 #define configTEX_S_C_B_SRAM ( 0x07UL )
183 #endif
184
185 #define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL )
186 #define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL )
187 #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
188 #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
189 #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
190 #define portFIRST_CONFIGURABLE_REGION ( 0UL )
191 #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
192 #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
193 #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
194
195 typedef struct MPU_REGION_REGISTERS
196 {
197 uint32_t ulRegionBaseAddress;
198 uint32_t ulRegionAttribute;
199 } xMPU_REGION_REGISTERS;
200
201 typedef struct MPU_REGION_SETTINGS
202 {
203 uint32_t ulRegionStartAddress;
204 uint32_t ulRegionEndAddress;
205 uint32_t ulRegionPermissions;
206 } xMPU_REGION_SETTINGS;
207
208 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
209
210 #ifndef configSYSTEM_CALL_STACK_SIZE
211 #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
212 #endif
213
214 typedef struct SYSTEM_CALL_STACK_INFO
215 {
216 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
217 uint32_t * pulSystemCallStack;
218 uint32_t * pulTaskStack;
219 uint32_t ulLinkRegisterAtSystemCallEntry;
220 } xSYSTEM_CALL_STACK_INFO;
221
222 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
223
224 #define MAX_CONTEXT_SIZE ( 52 )
225
226 /* Size of an Access Control List (ACL) entry in bits. */
227 #define portACL_ENTRY_SIZE_BITS ( 32U )
228
229 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
230 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
231 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
232
233 typedef struct MPU_SETTINGS
234 {
235 xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
236 xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
237 uint32_t ulContext[ MAX_CONTEXT_SIZE ];
238 uint32_t ulTaskFlags;
239
240 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
241 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
242 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
243 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
244 #endif
245 #endif
246 } xMPU_SETTINGS;
247
248 /* Architecture specifics. */
249 #define portSTACK_GROWTH ( -1 )
250 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
251 #define portBYTE_ALIGNMENT 8
252 /*-----------------------------------------------------------*/
253
254 /* SVC numbers for various services. */
255 #define portSVC_START_SCHEDULER 100
256 #define portSVC_YIELD 101
257 #define portSVC_RAISE_PRIVILEGE 102
258 #define portSVC_SYSTEM_CALL_EXIT 103
259
260 /* Scheduler utilities. */
261
262 #define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" )
263 #define portYIELD_WITHIN_API() \
264 { \
265 /* Set a PendSV to request a context switch. */ \
266 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
267 __DSB(); \
268 __ISB(); \
269 }
270
271 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
272 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
273 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
274 do \
275 { \
276 if( xSwitchRequired != pdFALSE ) \
277 { \
278 traceISR_EXIT_TO_SCHEDULER(); \
279 portYIELD_WITHIN_API(); \
280 } \
281 else \
282 { \
283 traceISR_EXIT(); \
284 } \
285 } while( 0 )
286 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
287 /*-----------------------------------------------------------*/
288
289 /* Architecture specific optimisations. */
290 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
291 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
292 #endif
293
294 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
295
296 /* Check the configuration. */
297 #if ( configMAX_PRIORITIES > 32 )
298 #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
299 #endif
300
301 /* Store/clear the ready priorities in a bit map. */
302 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
303 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
304
305 /*-----------------------------------------------------------*/
306
307 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
308
309 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
310 /*-----------------------------------------------------------*/
311
312 /* Critical section management. */
313 extern void vPortEnterCritical( void );
314 extern void vPortExitCritical( void );
315
316 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
317 #define portDISABLE_INTERRUPTS() \
318 { \
319 __disable_interrupt(); \
320 __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
321 __DSB(); \
322 __ISB(); \
323 __enable_interrupt(); \
324 }
325 #else
326 #define portDISABLE_INTERRUPTS() \
327 { \
328 __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
329 __DSB(); \
330 __ISB(); \
331 }
332 #endif /* if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) */
333
334 #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
335 #define portENTER_CRITICAL() vPortEnterCritical()
336 #define portEXIT_CRITICAL() vPortExitCritical()
337 #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
338 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
339 /*-----------------------------------------------------------*/
340
341 /* Task function macros as described on the FreeRTOS.org WEB site. These are
342 * not necessary for to use this port. They are defined so the common demo files
343 * (which build with all the ports) will build. */
344 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
345 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
346 /*-----------------------------------------------------------*/
347
348 #ifdef configASSERT
349 void vPortValidateInterruptPriority( void );
350 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
351 #endif
352
353 /* portNOP() is not required by this port. */
354 #define portNOP()
355
356 #define portINLINE __inline
357
358 #ifndef portFORCE_INLINE
359 #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
360 #endif
361
362 /*-----------------------------------------------------------*/
363
xPortIsInsideInterrupt(void)364 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
365 {
366 uint32_t ulCurrentInterrupt;
367 BaseType_t xReturn;
368
369 /* Obtain the number of the currently executing interrupt. */
370 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
371
372 if( ulCurrentInterrupt == 0 )
373 {
374 xReturn = pdFALSE;
375 }
376 else
377 {
378 xReturn = pdTRUE;
379 }
380
381 return xReturn;
382 }
383
384
385 /*-----------------------------------------------------------*/
386
387 extern BaseType_t xIsPrivileged( void );
388 extern void vResetPrivilege( void );
389 extern void vPortSwitchToUserMode( void );
390
391 /**
392 * @brief Checks whether or not the processor is privileged.
393 *
394 * @return 1 if the processor is already privileged, 0 otherwise.
395 */
396 #define portIS_PRIVILEGED() xIsPrivileged()
397
398 /**
399 * @brief Raise an SVC request to raise privilege.
400 */
401 #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
402
403 /**
404 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
405 * register.
406 */
407 #define portRESET_PRIVILEGE() vResetPrivilege()
408
409 /**
410 * @brief Make a task unprivileged.
411 *
412 * It must be called from privileged tasks only. Calling it from unprivileged
413 * task will result in a memory protection fault.
414 */
415 #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
416 /*-----------------------------------------------------------*/
417
418 extern BaseType_t xPortIsTaskPrivileged( void );
419
420 /**
421 * @brief Checks whether or not the calling task is privileged.
422 *
423 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
424 */
425 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
426 /*-----------------------------------------------------------*/
427
428 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
429 #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
430 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
431 #endif
432 /*-----------------------------------------------------------*/
433
434 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
435 * the source code because to do so would cause other compilers to generate
436 * warnings. */
437 #pragma diag_suppress=Pe191
438 #pragma diag_suppress=Pa082
439 #pragma diag_suppress=Be006
440 /*-----------------------------------------------------------*/
441
442 /* *INDENT-OFF* */
443 #ifdef __cplusplus
444 }
445 #endif
446 /* *INDENT-ON* */
447
448 #endif /* PORTMACRO_H */
449
