1/*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29#include <FreeRTOSConfig.h>
30
31    RSEG    CODE:CODE(2)
32    thumb
33
34    EXTERN pxCurrentTCB
35    EXTERN vTaskSwitchContext
36
37    PUBLIC xPortPendSVHandler
38    PUBLIC vPortSVCHandler
39    PUBLIC vPortStartFirstTask
40    PUBLIC vPortEnableVFP
41
42
43/*-----------------------------------------------------------*/
44
45xPortPendSVHandler:
46    mrs r0, psp
47    isb
48    /* Get the location of the current TCB. */
49    ldr r3, =pxCurrentTCB
50    ldr r2, [r3]
51
52    /* Is the task using the FPU context?  If so, push high vfp registers. */
53    tst r14, #0x10
54    it eq
55    vstmdbeq r0!, {s16-s31}
56
57    /* Save the core registers. */
58    stmdb r0!, {r4-r11, r14}
59
60    /* Save the new top of stack into the first member of the TCB. */
61    str r0, [r2]
62
63    stmdb sp!, {r0, r3}
64    mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
65    msr basepri, r0
66    dsb
67    isb
68    bl vTaskSwitchContext
69    mov r0, #0
70    msr basepri, r0
71    ldmia sp!, {r0, r3}
72
73    /* The first item in pxCurrentTCB is the task top of stack. */
74    ldr r1, [r3]
75    ldr r0, [r1]
76
77    /* Pop the core registers. */
78    ldmia r0!, {r4-r11, r14}
79
80    /* Is the task using the FPU context?  If so, pop the high vfp registers
81    too. */
82    tst r14, #0x10
83    it eq
84    vldmiaeq r0!, {s16-s31}
85
86    msr psp, r0
87    isb
88    #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
89        #if WORKAROUND_PMU_CM001 == 1
90            push { r14 }
91            pop { pc }
92        #endif
93    #endif
94
95    bx r14
96
97
98/*-----------------------------------------------------------*/
99
100vPortSVCHandler:
101    /* Get the location of the current TCB. */
102    ldr r3, =pxCurrentTCB
103    ldr r1, [r3]
104    ldr r0, [r1]
105    /* Pop the core registers. */
106    ldmia r0!, {r4-r11, r14}
107    msr psp, r0
108    isb
109    mov r0, #0
110    msr basepri, r0
111    bx r14
112
113/*-----------------------------------------------------------*/
114
115vPortStartFirstTask
116    /* Use the NVIC offset register to locate the stack. */
117    ldr r0, =0xE000ED08
118    ldr r0, [r0]
119    ldr r0, [r0]
120    /* Set the msp back to the start of the stack. */
121    msr msp, r0
122    /* Clear the bit that indicates the FPU is in use in case the FPU was used
123    before the scheduler was started - which would otherwise result in the
124    unnecessary leaving of space in the SVC stack for lazy saving of FPU
125    registers. */
126    mov r0, #0
127    msr control, r0
128    /* Call SVC to start the first task. */
129    cpsie i
130    cpsie f
131    dsb
132    isb
133    svc 0
134
135/*-----------------------------------------------------------*/
136
137vPortEnableVFP:
138    /* The FPU enable bits are in the CPACR. */
139    ldr.w r0, =0xE000ED88
140    ldr r1, [r0]
141
142    /* Enable CP10 and CP11 coprocessors, then save back. */
143    orr r1, r1, #( 0xf << 20 )
144    str r1, [r0]
145    bx  r14
146
147
148
149    END
150