1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33
34 /* *INDENT-OFF* */
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 /* *INDENT-ON* */
39
40 /*-----------------------------------------------------------
41 * Port specific definitions.
42 *
43 * The settings in this file configure FreeRTOS correctly for the
44 * given hardware and compiler.
45 *
46 * These settings should not be altered.
47 *-----------------------------------------------------------
48 */
49
50 /* Type definitions. */
51 #define portCHAR char
52 #define portFLOAT float
53 #define portDOUBLE double
54 #define portLONG long
55 #define portSHORT short
56 #define portSTACK_TYPE uint32_t
57 #define portBASE_TYPE long
58
59 typedef portSTACK_TYPE StackType_t;
60 typedef long BaseType_t;
61 typedef unsigned long UBaseType_t;
62
63 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
64 typedef uint16_t TickType_t;
65 #define portMAX_DELAY ( TickType_t ) 0xffff
66 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
67 typedef uint32_t TickType_t;
68 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
69
70 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
71 * not need to be guarded with a critical section. */
72 #define portTICK_TYPE_IS_ATOMIC 1
73 #else
74 #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width."
75 #endif
76
77 /* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
78 * and r0p1 cores. */
79 #ifndef configENABLE_ERRATA_837070_WORKAROUND
80 #define configENABLE_ERRATA_837070_WORKAROUND 0
81 #endif
82 /*-----------------------------------------------------------*/
83
84 /* MPU specific constants. */
85 #define portUSING_MPU_WRAPPERS 1
86 #define portPRIVILEGE_BIT ( 0x80000000UL )
87
88 #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
89 #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
90 #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
91 #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
92 #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
93 #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
94 #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
95
96 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
97 * Register (RASR). */
98 #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
99 #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
100
101 /* MPU settings that can be overriden in FreeRTOSConfig.h. */
102 #ifndef configTOTAL_MPU_REGIONS
103 /* Define to 8 for backward compatibility. */
104 #define configTOTAL_MPU_REGIONS ( 8UL )
105 #endif
106
107 /*
108 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
109 * memory type, and where necessary the cacheable and shareable properties
110 * of the memory region.
111 *
112 * The TEX, C, and B bits together indicate the memory type of the region,
113 * and:
114 * - For Normal memory, the cacheable properties of the region.
115 * - For Device memory, whether the region is shareable.
116 *
117 * For Normal memory regions, the S bit indicates whether the region is
118 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
119 *
120 * See the following two tables for setting TEX, S, C and B bits for
121 * unprivileged flash, privileged flash and privileged RAM regions.
122 *
123 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
124 | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
125 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
126 | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
127 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
128 | 000 | 0 | 1 | Device | Shared device | Shareable |
129 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
130 | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
131 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
132 | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
133 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
134 | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
135 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
136 | 001 | 0 | 1 | Reserved | Reserved | Reserved |
137 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
138 | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
139 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
140 | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
141 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
142 | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
143 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
144 | 010 | 0 | 1 | Reserved | Reserved | Reserved |
145 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
146 | 010 | 1 | X | Reserved | Reserved | Reserved |
147 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
148 | 011 | X | X | Reserved | Reserved | Reserved |
149 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
150 | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
151 | | | | | outer cacheability rules that must be exported on the | |
152 | | | | | bus. See the table below for the cacheability policy | |
153 | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
154 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
155 |
156 +-----------------------------------------+----------------------------------------+
157 | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
158 +-----------------------------------------+----------------------------------------+
159 | 00 | Non-cacheable |
160 +-----------------------------------------+----------------------------------------+
161 | 01 | Write-back, write and read allocate |
162 +-----------------------------------------+----------------------------------------+
163 | 10 | Write-through, no write allocate |
164 +-----------------------------------------+----------------------------------------+
165 | 11 | Write-back, no write allocate |
166 +-----------------------------------------+----------------------------------------+
167 */
168
169 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
170 * region. */
171 #ifndef configTEX_S_C_B_FLASH
172 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
173 #define configTEX_S_C_B_FLASH ( 0x07UL )
174 #endif
175
176 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
177 * region. */
178 #ifndef configTEX_S_C_B_SRAM
179 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
180 #define configTEX_S_C_B_SRAM ( 0x07UL )
181 #endif
182
183 #define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL )
184 #define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL )
185 #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
186 #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
187 #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
188 #define portFIRST_CONFIGURABLE_REGION ( 0UL )
189 #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
190 #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
191 #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
192
193 typedef struct MPU_REGION_REGISTERS
194 {
195 uint32_t ulRegionBaseAddress;
196 uint32_t ulRegionAttribute;
197 } xMPU_REGION_REGISTERS;
198
199 typedef struct MPU_REGION_SETTINGS
200 {
201 uint32_t ulRegionStartAddress;
202 uint32_t ulRegionEndAddress;
203 uint32_t ulRegionPermissions;
204 } xMPU_REGION_SETTINGS;
205
206 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
207
208 #ifndef configSYSTEM_CALL_STACK_SIZE
209 #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2."
210 #endif
211
212 typedef struct SYSTEM_CALL_STACK_INFO
213 {
214 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
215 uint32_t * pulSystemCallStack;
216 uint32_t * pulTaskStack;
217 uint32_t ulLinkRegisterAtSystemCallEntry;
218 } xSYSTEM_CALL_STACK_INFO;
219
220 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
221
222 #define MAX_CONTEXT_SIZE ( 52 )
223
224 /* Size of an Access Control List (ACL) entry in bits. */
225 #define portACL_ENTRY_SIZE_BITS ( 32U )
226
227 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
228 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
229 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
230
231 typedef struct MPU_SETTINGS
232 {
233 xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
234 xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
235 uint32_t ulContext[ MAX_CONTEXT_SIZE ];
236 uint32_t ulTaskFlags;
237
238 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
239 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
240 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
241 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
242 #endif
243 #endif
244 } xMPU_SETTINGS;
245
246 /* Architecture specifics. */
247 #define portSTACK_GROWTH ( -1 )
248 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
249 #define portBYTE_ALIGNMENT 8
250 #define portDONT_DISCARD __attribute__( ( used ) )
251 /*-----------------------------------------------------------*/
252
253 /* SVC numbers for various services. */
254 #define portSVC_START_SCHEDULER 100
255 #define portSVC_YIELD 101
256 #define portSVC_RAISE_PRIVILEGE 102
257 #define portSVC_SYSTEM_CALL_EXIT 103
258
259 /* Scheduler utilities. */
260
261 #define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" )
262 #define portYIELD_WITHIN_API() \
263 { \
264 /* Set a PendSV to request a context switch. */ \
265 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
266 \
267 /* Barriers are normally not required but do ensure the code is completely \
268 * within the specified behaviour for the architecture. */ \
269 __asm volatile ( "dsb" ::: "memory" ); \
270 __asm volatile ( "isb" ); \
271 }
272
273 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
274 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
275 #define portEND_SWITCHING_ISR( xSwitchRequired ) \
276 do \
277 { \
278 if( xSwitchRequired ) \
279 { \
280 traceISR_EXIT_TO_SCHEDULER(); \
281 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
282 } \
283 else \
284 { \
285 traceISR_EXIT(); \
286 } \
287 } while( 0 )
288 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
289 /*-----------------------------------------------------------*/
290
291 /* Critical section management. */
292 extern void vPortEnterCritical( void );
293 extern void vPortExitCritical( void );
294 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
295 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
296 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
297 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
298 #define portENTER_CRITICAL() vPortEnterCritical()
299 #define portEXIT_CRITICAL() vPortExitCritical()
300
301 /*-----------------------------------------------------------*/
302
303 /* Task function macros as described on the FreeRTOS.org WEB site. These are
304 * not necessary for to use this port. They are defined so the common demo files
305 * (which build with all the ports) will build. */
306 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
307 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
308 /*-----------------------------------------------------------*/
309
310 /* Architecture specific optimisations. */
311 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
312 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
313 #endif
314
315 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
316
317 /* Generic helper function. */
ucPortCountLeadingZeros(uint32_t ulBitmap)318 __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
319 {
320 uint8_t ucReturn;
321
322 __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
323
324 return ucReturn;
325 }
326
327 /* Check the configuration. */
328 #if ( configMAX_PRIORITIES > 32 )
329 #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
330 #endif
331
332 /* Store/clear the ready priorities in a bit map. */
333 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
334 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
335
336 /*-----------------------------------------------------------*/
337
338 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
339
340 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
341
342 /*-----------------------------------------------------------*/
343
344 #ifdef configASSERT
345 void vPortValidateInterruptPriority( void );
346 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
347 #endif
348
349 /* portNOP() is not required by this port. */
350 #define portNOP()
351
352 #define portINLINE __inline
353
354 #ifndef portFORCE_INLINE
355 #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
356 #endif
357 /*-----------------------------------------------------------*/
358
359 extern BaseType_t xIsPrivileged( void );
360 extern void vResetPrivilege( void );
361 extern void vPortSwitchToUserMode( void );
362
363 /**
364 * @brief Checks whether or not the processor is privileged.
365 *
366 * @return 1 if the processor is already privileged, 0 otherwise.
367 */
368 #define portIS_PRIVILEGED() xIsPrivileged()
369
370 /**
371 * @brief Raise an SVC request to raise privilege.
372 */
373 #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
374
375 /**
376 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
377 * register.
378 */
379 #define portRESET_PRIVILEGE() vResetPrivilege()
380
381 /**
382 * @brief Make a task unprivileged.
383 *
384 * It must be called from privileged tasks only. Calling it from unprivileged
385 * task will result in a memory protection fault.
386 */
387 #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
388 /*-----------------------------------------------------------*/
389
390 extern BaseType_t xPortIsTaskPrivileged( void );
391
392 /**
393 * @brief Checks whether or not the calling task is privileged.
394 *
395 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
396 */
397 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
398 /*-----------------------------------------------------------*/
399
xPortIsInsideInterrupt(void)400 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
401 {
402 uint32_t ulCurrentInterrupt;
403 BaseType_t xReturn;
404
405 /* Obtain the number of the currently executing interrupt. */
406 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
407
408 if( ulCurrentInterrupt == 0 )
409 {
410 xReturn = pdFALSE;
411 }
412 else
413 {
414 xReturn = pdTRUE;
415 }
416
417 return xReturn;
418 }
419
420 /*-----------------------------------------------------------*/
421
vPortRaiseBASEPRI(void)422 portFORCE_INLINE static void vPortRaiseBASEPRI( void )
423 {
424 uint32_t ulNewBASEPRI;
425
426 __asm volatile
427 (
428 " mov %0, %1 \n"
429 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
430 " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
431 #endif
432 " msr basepri, %0 \n"
433 " isb \n"
434 " dsb \n"
435 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
436 " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
437 #endif
438 : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
439 );
440 }
441
442 /*-----------------------------------------------------------*/
443
ulPortRaiseBASEPRI(void)444 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
445 {
446 uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
447
448 __asm volatile
449 (
450 " mrs %0, basepri \n"
451 " mov %1, %2 \n"
452 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
453 " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
454 #endif
455 " msr basepri, %1 \n"
456 " isb \n"
457 " dsb \n"
458 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
459 " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
460 #endif
461 : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
462 );
463
464 /* This return will not be reached but is necessary to prevent compiler
465 * warnings. */
466 return ulOriginalBASEPRI;
467 }
468 /*-----------------------------------------------------------*/
469
vPortSetBASEPRI(uint32_t ulNewMaskValue)470 portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
471 {
472 __asm volatile
473 (
474 " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory"
475 );
476 }
477 /*-----------------------------------------------------------*/
478
479 #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
480
481 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
482 #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
483 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
484 #endif
485 /*-----------------------------------------------------------*/
486
487 /* *INDENT-OFF* */
488 #ifdef __cplusplus
489 }
490 #endif
491 /* *INDENT-ON* */
492
493 #endif /* PORTMACRO_H */
494
