1 /* 2 * FreeRTOS Kernel V10.6.2 3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * https://www.FreeRTOS.org 25 * https://github.com/FreeRTOS 26 * 27 */ 28 29 30 #ifndef PORTMACRO_H 31 #define PORTMACRO_H 32 33 /* *INDENT-OFF* */ 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 /* *INDENT-ON* */ 38 39 /*----------------------------------------------------------- 40 * Port specific definitions. 41 * 42 * The settings in this file configure FreeRTOS correctly for the 43 * given hardware and compiler. 44 * 45 * These settings should not be altered. 46 *----------------------------------------------------------- 47 */ 48 49 /* Type definitions. */ 50 #define portCHAR char 51 #define portFLOAT float 52 #define portDOUBLE double 53 #define portLONG long 54 #define portSHORT short 55 #define portSTACK_TYPE uint32_t 56 #define portBASE_TYPE long 57 58 typedef portSTACK_TYPE StackType_t; 59 typedef long BaseType_t; 60 typedef unsigned long UBaseType_t; 61 62 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) 63 typedef uint16_t TickType_t; 64 #define portMAX_DELAY ( TickType_t ) 0xffff 65 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) 66 typedef uint32_t TickType_t; 67 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 68 69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do 70 * not need to be guarded with a critical section. */ 71 #define portTICK_TYPE_IS_ATOMIC 1 72 #else 73 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. 74 #endif 75 /*-----------------------------------------------------------*/ 76 77 /* Architecture specifics. */ 78 #define portSTACK_GROWTH ( -1 ) 79 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 80 #define portBYTE_ALIGNMENT 8 81 82 /* Constants used with memory barrier intrinsics. */ 83 #define portSY_FULL_READ_WRITE ( 15 ) 84 85 /*-----------------------------------------------------------*/ 86 87 /* Scheduler utilities. */ 88 #define portYIELD() \ 89 { \ 90 /* Set a PendSV to request a context switch. */ \ 91 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ 92 \ 93 /* Barriers are normally not required but do ensure the code is completely \ 94 * within the specified behaviour for the architecture. */ \ 95 __dsb( portSY_FULL_READ_WRITE ); \ 96 __isb( portSY_FULL_READ_WRITE ); \ 97 } 98 /*-----------------------------------------------------------*/ 99 100 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) 101 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) 102 #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) 103 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) 104 /*-----------------------------------------------------------*/ 105 106 /* Critical section management. */ 107 extern void vPortEnterCritical( void ); 108 extern void vPortExitCritical( void ); 109 110 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() 111 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) 112 #define portENTER_CRITICAL() vPortEnterCritical() 113 #define portEXIT_CRITICAL() vPortExitCritical() 114 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() 115 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) 116 117 /*-----------------------------------------------------------*/ 118 119 /* Tickless idle/low power functionality. */ 120 #ifndef portSUPPRESS_TICKS_AND_SLEEP 121 extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); 122 #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) 123 #endif 124 /*-----------------------------------------------------------*/ 125 126 /* Port specific optimisations. */ 127 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION 128 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 129 #endif 130 131 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 132 133 /* Check the configuration. */ 134 #if ( configMAX_PRIORITIES > 32 ) 135 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. 136 #endif 137 138 /* Store/clear the ready priorities in a bit map. */ 139 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) 140 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) 141 142 /*-----------------------------------------------------------*/ 143 144 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) 145 146 #endif /* taskRECORD_READY_PRIORITY */ 147 /*-----------------------------------------------------------*/ 148 149 /* Task function macros as described on the FreeRTOS.org WEB site. These are 150 * not necessary for to use this port. They are defined so the common demo files 151 * (which build with all the ports) will build. */ 152 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 153 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 154 /*-----------------------------------------------------------*/ 155 156 #ifdef configASSERT 157 void vPortValidateInterruptPriority( void ); 158 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() 159 #endif 160 161 /* portNOP() is not required by this port. */ 162 #define portNOP() 163 164 #define portINLINE __inline 165 166 #ifndef portFORCE_INLINE 167 #define portFORCE_INLINE __forceinline 168 #endif 169 170 /*-----------------------------------------------------------*/ 171 vPortSetBASEPRI(uint32_t ulBASEPRI)172 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) 173 { 174 __asm 175 { 176 /* Barrier instructions are not used as this function is only used to 177 * lower the BASEPRI value. */ 178 /* *INDENT-OFF* */ 179 msr basepri, ulBASEPRI 180 /* *INDENT-ON* */ 181 } 182 } 183 /*-----------------------------------------------------------*/ 184 vPortRaiseBASEPRI(void)185 static portFORCE_INLINE void vPortRaiseBASEPRI( void ) 186 { 187 uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; 188 189 __asm 190 { 191 /* Set BASEPRI to the max syscall priority to effect a critical 192 * section. */ 193 /* *INDENT-OFF* */ 194 cpsid i 195 msr basepri, ulNewBASEPRI 196 dsb 197 isb 198 cpsie i 199 /* *INDENT-ON* */ 200 } 201 } 202 /*-----------------------------------------------------------*/ 203 vPortClearBASEPRIFromISR(void)204 static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) 205 { 206 __asm 207 { 208 /* Set BASEPRI to 0 so no interrupts are masked. This function is only 209 * used to lower the mask in an interrupt, so memory barriers are not 210 * used. */ 211 /* *INDENT-OFF* */ 212 msr basepri, # 0 213 /* *INDENT-ON* */ 214 } 215 } 216 /*-----------------------------------------------------------*/ 217 ulPortRaiseBASEPRI(void)218 static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) 219 { 220 uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; 221 222 __asm 223 { 224 /* Set BASEPRI to the max syscall priority to effect a critical 225 * section. */ 226 /* *INDENT-OFF* */ 227 mrs ulReturn, basepri 228 cpsid i 229 msr basepri, ulNewBASEPRI 230 dsb 231 isb 232 cpsie i 233 /* *INDENT-ON* */ 234 } 235 236 return ulReturn; 237 } 238 /*-----------------------------------------------------------*/ 239 xPortIsInsideInterrupt(void)240 static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) 241 { 242 uint32_t ulCurrentInterrupt; 243 BaseType_t xReturn; 244 245 /* Obtain the number of the currently executing interrupt. */ 246 __asm 247 { 248 /* *INDENT-OFF* */ 249 mrs ulCurrentInterrupt, ipsr 250 /* *INDENT-ON* */ 251 } 252 253 if( ulCurrentInterrupt == 0 ) 254 { 255 xReturn = pdFALSE; 256 } 257 else 258 { 259 xReturn = pdTRUE; 260 } 261 262 return xReturn; 263 } 264 265 /* *INDENT-OFF* */ 266 #ifdef __cplusplus 267 } 268 #endif 269 /* *INDENT-ON* */ 270 271 #endif /* PORTMACRO_H */ 272