1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM7 port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #ifndef __TARGET_FPU_VFP
38 #error This port can only be used when the project options are configured to enable hardware floating point support.
39 #endif
40
41 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
42 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
43 #endif
44
45 /* The __weak attribute does not work as you might expect with the Keil tools
46 * so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
47 * the application writer wants to provide their own implementation of
48 * vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
49 * is defined. */
50 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
51 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
52 #endif
53
54 /* Constants required to manipulate the core. Registers first... */
55 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
56 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
57 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
58 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
59 /* ...then bits in the registers. */
60 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
61 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
62 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
63 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
64 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
65 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
66 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
67
68 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
69 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
70 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
71
72 /* Constants required to check the validity of an interrupt priority. */
73 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
74 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
75 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
76 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
77 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
78 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
79 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
80 #define portPRIGROUP_SHIFT ( 8UL )
81
82 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
83 #define portVECTACTIVE_MASK ( 0xFFUL )
84
85 /* Constants required to manipulate the VFP. */
86 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
87 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
88
89 /* Constants required to set up the initial stack. */
90 #define portINITIAL_XPSR ( 0x01000000 )
91 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
92
93 /* The systick is a 24-bit counter. */
94 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
95
96 /* A fiddle factor to estimate the number of SysTick counts that would have
97 * occurred while the SysTick counter is stopped during tickless idle
98 * calculations. */
99 #define portMISSED_COUNTS_FACTOR ( 94UL )
100
101 /* For strict compliance with the Cortex-M spec the task start address should
102 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
103 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
104
105 /* Let the user override the default SysTick clock rate. If defined by the
106 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
107 * configuration register. */
108 #ifndef configSYSTICK_CLOCK_HZ
109 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
110 /* Ensure the SysTick is clocked at the same frequency as the core. */
111 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
112 #else
113 /* Select the option to clock SysTick not at the same frequency as the core. */
114 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
115 #endif
116
117 /*
118 * Setup the timer to generate the tick interrupts. The implementation in this
119 * file is weak to allow application writers to change the timer used to
120 * generate the tick interrupt.
121 */
122 void vPortSetupTimerInterrupt( void );
123
124 /*
125 * Exception handlers.
126 */
127 void xPortPendSVHandler( void );
128 void xPortSysTickHandler( void );
129 void vPortSVCHandler( void );
130
131 /*
132 * Start first task is a separate function so it can be tested in isolation.
133 */
134 static void prvStartFirstTask( void );
135
136 /*
137 * Functions defined in portasm.s to enable the VFP.
138 */
139 static void prvEnableVFP( void );
140
141 /*
142 * Used to catch tasks that attempt to return from their implementing function.
143 */
144 static void prvTaskExitError( void );
145
146 /*-----------------------------------------------------------*/
147
148 /* Each task maintains its own interrupt status in the critical nesting
149 * variable. */
150 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
151
152 /*
153 * The number of SysTick increments that make up one tick period.
154 */
155 #if ( configUSE_TICKLESS_IDLE == 1 )
156 static uint32_t ulTimerCountsForOneTick = 0;
157 #endif /* configUSE_TICKLESS_IDLE */
158
159 /*
160 * The maximum number of tick periods that can be suppressed is limited by the
161 * 24 bit resolution of the SysTick timer.
162 */
163 #if ( configUSE_TICKLESS_IDLE == 1 )
164 static uint32_t xMaximumPossibleSuppressedTicks = 0;
165 #endif /* configUSE_TICKLESS_IDLE */
166
167 /*
168 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
169 * power functionality only.
170 */
171 #if ( configUSE_TICKLESS_IDLE == 1 )
172 static uint32_t ulStoppedTimerCompensation = 0;
173 #endif /* configUSE_TICKLESS_IDLE */
174
175 /*
176 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
177 * FreeRTOS API functions are not called from interrupts that have been assigned
178 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
179 */
180 #if ( configASSERT_DEFINED == 1 )
181 static uint8_t ucMaxSysCallPriority = 0;
182 static uint32_t ulMaxPRIGROUPValue = 0;
183 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
184 #endif /* configASSERT_DEFINED */
185
186 /*-----------------------------------------------------------*/
187
188 /*
189 * See header file for description.
190 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)191 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
192 TaskFunction_t pxCode,
193 void * pvParameters )
194 {
195 /* Simulate the stack frame as it would be created by a context switch
196 * interrupt. */
197
198 /* Offset added to account for the way the MCU uses the stack on entry/exit
199 * of interrupts, and to ensure alignment. */
200 pxTopOfStack--;
201
202 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
203 pxTopOfStack--;
204 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
205 pxTopOfStack--;
206 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
207
208 /* Save code space by skipping register initialisation. */
209 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
210 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
211
212 /* A save method is being used that requires each task to maintain its
213 * own exec return value. */
214 pxTopOfStack--;
215 *pxTopOfStack = portINITIAL_EXC_RETURN;
216
217 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
218
219 return pxTopOfStack;
220 }
221 /*-----------------------------------------------------------*/
222
prvTaskExitError(void)223 static void prvTaskExitError( void )
224 {
225 /* A function that implements a task must not exit or attempt to return to
226 * its caller as there is nothing to return to. If a task wants to exit it
227 * should instead call vTaskDelete( NULL ).
228 *
229 * Artificially force an assert() to be triggered if configASSERT() is
230 * defined, then stop here so application writers can catch the error. */
231 configASSERT( uxCriticalNesting == ~0UL );
232 portDISABLE_INTERRUPTS();
233
234 for( ; ; )
235 {
236 }
237 }
238 /*-----------------------------------------------------------*/
239
vPortSVCHandler(void)240 __asm void vPortSVCHandler( void )
241 {
242 /* *INDENT-OFF* */
243 PRESERVE8
244
245 /* Get the location of the current TCB. */
246 ldr r3, =pxCurrentTCB
247 ldr r1, [ r3 ]
248 ldr r0, [ r1 ]
249 /* Pop the core registers. */
250 ldmia r0!, { r4-r11, r14 }
251 msr psp, r0
252 isb
253 mov r0, #0
254 msr basepri, r0
255 bx r14
256 /* *INDENT-ON* */
257 }
258 /*-----------------------------------------------------------*/
259
prvStartFirstTask(void)260 __asm void prvStartFirstTask( void )
261 {
262 /* *INDENT-OFF* */
263 PRESERVE8
264
265 /* Use the NVIC offset register to locate the stack. */
266 ldr r0, =0xE000ED08
267 ldr r0, [ r0 ]
268 ldr r0, [ r0 ]
269 /* Set the msp back to the start of the stack. */
270 msr msp, r0
271
272 /* Clear the bit that indicates the FPU is in use in case the FPU was used
273 * before the scheduler was started - which would otherwise result in the
274 * unnecessary leaving of space in the SVC stack for lazy saving of FPU
275 * registers. */
276 mov r0, #0
277 msr control, r0
278 /* Globally enable interrupts. */
279 cpsie i
280 cpsie f
281 dsb
282 isb
283 /* Call SVC to start the first task. */
284 svc 0
285 nop
286 nop
287 /* *INDENT-ON* */
288 }
289 /*-----------------------------------------------------------*/
290
prvEnableVFP(void)291 __asm void prvEnableVFP( void )
292 {
293 /* *INDENT-OFF* */
294 PRESERVE8
295
296 /* The FPU enable bits are in the CPACR. */
297 ldr.w r0, =0xE000ED88
298 ldr r1, [ r0 ]
299
300 /* Enable CP10 and CP11 coprocessors, then save back. */
301 orr r1, r1, #( 0xf << 20 )
302 str r1, [ r0 ]
303 bx r14
304 nop
305 /* *INDENT-ON* */
306 }
307 /*-----------------------------------------------------------*/
308
309 /*
310 * See header file for description.
311 */
xPortStartScheduler(void)312 BaseType_t xPortStartScheduler( void )
313 {
314 #if ( configASSERT_DEFINED == 1 )
315 {
316 volatile uint8_t ucOriginalPriority;
317 volatile uint32_t ulImplementedPrioBits = 0;
318 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
319 volatile uint8_t ucMaxPriorityValue;
320
321 /* Determine the maximum priority from which ISR safe FreeRTOS API
322 * functions can be called. ISR safe functions are those that end in
323 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
324 * ensure interrupt entry is as fast and simple as possible.
325 *
326 * Save the interrupt priority value that is about to be clobbered. */
327 ucOriginalPriority = *pucFirstUserPriorityRegister;
328
329 /* Determine the number of priority bits available. First write to all
330 * possible bits. */
331 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
332
333 /* Read the value back to see how many bits stuck. */
334 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
335
336 /* Use the same mask on the maximum system call priority. */
337 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
338
339 /* Check that the maximum system call priority is nonzero after
340 * accounting for the number of priority bits supported by the
341 * hardware. A priority of 0 is invalid because setting the BASEPRI
342 * register to 0 unmasks all interrupts, and interrupts with priority 0
343 * cannot be masked using BASEPRI.
344 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
345 configASSERT( ucMaxSysCallPriority );
346
347 /* Check that the bits not implemented in hardware are zero in
348 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
349 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
350
351 /* Calculate the maximum acceptable priority group value for the number
352 * of bits read back. */
353
354 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
355 {
356 ulImplementedPrioBits++;
357 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
358 }
359
360 if( ulImplementedPrioBits == 8 )
361 {
362 /* When the hardware implements 8 priority bits, there is no way for
363 * the software to configure PRIGROUP to not have sub-priorities. As
364 * a result, the least significant bit is always used for sub-priority
365 * and there are 128 preemption priorities and 2 sub-priorities.
366 *
367 * This may cause some confusion in some cases - for example, if
368 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
369 * priority interrupts will be masked in Critical Sections as those
370 * are at the same preemption priority. This may appear confusing as
371 * 4 is higher (numerically lower) priority than
372 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
373 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
374 * to 4, this confusion does not happen and the behaviour remains the same.
375 *
376 * The following assert ensures that the sub-priority bit in the
377 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
378 * confusion. */
379 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
380 ulMaxPRIGROUPValue = 0;
381 }
382 else
383 {
384 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
385 }
386
387 /* Shift the priority group value back to its position within the AIRCR
388 * register. */
389 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
390 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
391
392 /* Restore the clobbered interrupt priority register to its original
393 * value. */
394 *pucFirstUserPriorityRegister = ucOriginalPriority;
395 }
396 #endif /* configASSERT_DEFINED */
397
398 /* Make PendSV and SysTick the lowest priority interrupts. */
399 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
400 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
401
402 /* Start the timer that generates the tick ISR. Interrupts are disabled
403 * here already. */
404 vPortSetupTimerInterrupt();
405
406 /* Initialise the critical nesting count ready for the first task. */
407 uxCriticalNesting = 0;
408
409 /* Ensure the VFP is enabled - it should be anyway. */
410 prvEnableVFP();
411
412 /* Lazy save always. */
413 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
414
415 /* Start the first task. */
416 prvStartFirstTask();
417
418 /* Should not get here! */
419 return 0;
420 }
421 /*-----------------------------------------------------------*/
422
vPortEndScheduler(void)423 void vPortEndScheduler( void )
424 {
425 /* Not implemented in ports where there is nothing to return to.
426 * Artificially force an assert. */
427 configASSERT( uxCriticalNesting == 1000UL );
428 }
429 /*-----------------------------------------------------------*/
430
vPortEnterCritical(void)431 void vPortEnterCritical( void )
432 {
433 portDISABLE_INTERRUPTS();
434 uxCriticalNesting++;
435
436 /* This is not the interrupt safe version of the enter critical function so
437 * assert() if it is being called from an interrupt context. Only API
438 * functions that end in "FromISR" can be used in an interrupt. Only assert if
439 * the critical nesting count is 1 to protect against recursive calls if the
440 * assert function also uses a critical section. */
441 if( uxCriticalNesting == 1 )
442 {
443 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
444 }
445 }
446 /*-----------------------------------------------------------*/
447
vPortExitCritical(void)448 void vPortExitCritical( void )
449 {
450 configASSERT( uxCriticalNesting );
451 uxCriticalNesting--;
452
453 if( uxCriticalNesting == 0 )
454 {
455 portENABLE_INTERRUPTS();
456 }
457 }
458 /*-----------------------------------------------------------*/
459
xPortPendSVHandler(void)460 __asm void xPortPendSVHandler( void )
461 {
462 extern uxCriticalNesting;
463 extern pxCurrentTCB;
464 extern vTaskSwitchContext;
465
466 /* *INDENT-OFF* */
467 PRESERVE8
468
469 mrs r0, psp
470 isb
471 /* Get the location of the current TCB. */
472 ldr r3, =pxCurrentTCB
473 ldr r2, [ r3 ]
474
475 /* Is the task using the FPU context? If so, push high vfp registers. */
476 tst r14, #0x10
477 it eq
478 vstmdbeq r0!, {s16-s31}
479
480 /* Save the core registers. */
481 stmdb r0!, {r4-r11, r14 }
482
483 /* Save the new top of stack into the first member of the TCB. */
484 str r0, [ r2 ]
485
486 stmdb sp!, { r0, r3 }
487 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
488 cpsid i
489 msr basepri, r0
490 dsb
491 isb
492 cpsie i
493 bl vTaskSwitchContext
494 mov r0, #0
495 msr basepri, r0
496 ldmia sp!, { r0, r3 }
497
498 /* The first item in pxCurrentTCB is the task top of stack. */
499 ldr r1, [ r3 ]
500 ldr r0, [ r1 ]
501
502 /* Pop the core registers. */
503 ldmia r0!, { r4-r11, r14 }
504
505 /* Is the task using the FPU context? If so, pop the high vfp registers
506 * too. */
507 tst r14, #0x10
508 it eq
509 vldmiaeq r0!, { s16-s31 }
510
511 msr psp, r0
512 isb
513 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
514 #if WORKAROUND_PMU_CM001 == 1
515 push { r14 }
516 pop { pc }
517 nop
518 #endif
519 #endif
520
521 bx r14
522 /* *INDENT-ON* */
523 }
524 /*-----------------------------------------------------------*/
525
xPortSysTickHandler(void)526 void xPortSysTickHandler( void )
527 {
528 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
529 * executes all interrupts must be unmasked. There is therefore no need to
530 * save and then restore the interrupt mask value as its value is already
531 * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
532 * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
533 vPortRaiseBASEPRI();
534 {
535 /* Increment the RTOS tick. */
536 if( xTaskIncrementTick() != pdFALSE )
537 {
538 /* A context switch is required. Context switching is performed in
539 * the PendSV interrupt. Pend the PendSV interrupt. */
540 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
541 }
542 }
543
544 vPortClearBASEPRIFromISR();
545 }
546 /*-----------------------------------------------------------*/
547
548 #if ( configUSE_TICKLESS_IDLE == 1 )
549
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)550 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
551 {
552 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
553 TickType_t xModifiableIdleTime;
554
555 /* Make sure the SysTick reload value does not overflow the counter. */
556 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
557 {
558 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
559 }
560
561 /* Enter a critical section but don't use the taskENTER_CRITICAL()
562 * method as that will mask interrupts that should exit sleep mode. */
563 __disable_irq();
564 __dsb( portSY_FULL_READ_WRITE );
565 __isb( portSY_FULL_READ_WRITE );
566
567 /* If a context switch is pending or a task is waiting for the scheduler
568 * to be unsuspended then abandon the low power entry. */
569 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
570 {
571 /* Re-enable interrupts - see comments above the __disable_irq()
572 * call above. */
573 __enable_irq();
574 }
575 else
576 {
577 /* Stop the SysTick momentarily. The time the SysTick is stopped for
578 * is accounted for as best it can be, but using the tickless mode will
579 * inevitably result in some tiny drift of the time maintained by the
580 * kernel with respect to calendar time. */
581 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
582
583 /* Use the SysTick current-value register to determine the number of
584 * SysTick decrements remaining until the next tick interrupt. If the
585 * current-value register is zero, then there are actually
586 * ulTimerCountsForOneTick decrements remaining, not zero, because the
587 * SysTick requests the interrupt when decrementing from 1 to 0. */
588 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
589
590 if( ulSysTickDecrementsLeft == 0 )
591 {
592 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
593 }
594
595 /* Calculate the reload value required to wait xExpectedIdleTime
596 * tick periods. -1 is used because this code normally executes part
597 * way through the first tick period. But if the SysTick IRQ is now
598 * pending, then clear the IRQ, suppressing the first tick, and correct
599 * the reload value to reflect that the second tick period is already
600 * underway. The expected idle time is always at least two ticks. */
601 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
602
603 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
604 {
605 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
606 ulReloadValue -= ulTimerCountsForOneTick;
607 }
608
609 if( ulReloadValue > ulStoppedTimerCompensation )
610 {
611 ulReloadValue -= ulStoppedTimerCompensation;
612 }
613
614 /* Set the new reload value. */
615 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
616
617 /* Clear the SysTick count flag and set the count value back to
618 * zero. */
619 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
620
621 /* Restart SysTick. */
622 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
623
624 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
625 * set its parameter to 0 to indicate that its implementation contains
626 * its own wait for interrupt or wait for event instruction, and so wfi
627 * should not be executed again. However, the original expected idle
628 * time variable must remain unmodified, so a copy is taken. */
629 xModifiableIdleTime = xExpectedIdleTime;
630 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
631
632 if( xModifiableIdleTime > 0 )
633 {
634 __dsb( portSY_FULL_READ_WRITE );
635 __wfi();
636 __isb( portSY_FULL_READ_WRITE );
637 }
638
639 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
640
641 /* Re-enable interrupts to allow the interrupt that brought the MCU
642 * out of sleep mode to execute immediately. See comments above
643 * the __disable_irq() call above. */
644 __enable_irq();
645 __dsb( portSY_FULL_READ_WRITE );
646 __isb( portSY_FULL_READ_WRITE );
647
648 /* Disable interrupts again because the clock is about to be stopped
649 * and interrupts that execute while the clock is stopped will increase
650 * any slippage between the time maintained by the RTOS and calendar
651 * time. */
652 __disable_irq();
653 __dsb( portSY_FULL_READ_WRITE );
654 __isb( portSY_FULL_READ_WRITE );
655
656 /* Disable the SysTick clock without reading the
657 * portNVIC_SYSTICK_CTRL_REG register to ensure the
658 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
659 * the time the SysTick is stopped for is accounted for as best it can
660 * be, but using the tickless mode will inevitably result in some tiny
661 * drift of the time maintained by the kernel with respect to calendar
662 * time*/
663 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
664
665 /* Determine whether the SysTick has already counted to zero. */
666 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
667 {
668 uint32_t ulCalculatedLoadValue;
669
670 /* The tick interrupt ended the sleep (or is now pending), and
671 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
672 * with whatever remains of the new tick period. */
673 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
674
675 /* Don't allow a tiny value, or values that have somehow
676 * underflowed because the post sleep hook did something
677 * that took too long or because the SysTick current-value register
678 * is zero. */
679 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
680 {
681 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
682 }
683
684 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
685
686 /* As the pending tick will be processed as soon as this
687 * function exits, the tick value maintained by the tick is stepped
688 * forward by one less than the time spent waiting. */
689 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
690 }
691 else
692 {
693 /* Something other than the tick interrupt ended the sleep. */
694
695 /* Use the SysTick current-value register to determine the
696 * number of SysTick decrements remaining until the expected idle
697 * time would have ended. */
698 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
699 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
700 {
701 /* If the SysTick is not using the core clock, the current-
702 * value register might still be zero here. In that case, the
703 * SysTick didn't load from the reload register, and there are
704 * ulReloadValue decrements remaining in the expected idle
705 * time, not zero. */
706 if( ulSysTickDecrementsLeft == 0 )
707 {
708 ulSysTickDecrementsLeft = ulReloadValue;
709 }
710 }
711 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
712
713 /* Work out how long the sleep lasted rounded to complete tick
714 * periods (not the ulReload value which accounted for part
715 * ticks). */
716 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
717
718 /* How many complete tick periods passed while the processor
719 * was waiting? */
720 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
721
722 /* The reload value is set to whatever fraction of a single tick
723 * period remains. */
724 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
725 }
726
727 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
728 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
729 * the SysTick is not using the core clock, temporarily configure it to
730 * use the core clock. This configuration forces the SysTick to load
731 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
732 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
733 * to receive the standard value immediately. */
734 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
735 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
736 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
737 {
738 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
739 }
740 #else
741 {
742 /* The temporary usage of the core clock has served its purpose,
743 * as described above. Resume usage of the other clock. */
744 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
745
746 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
747 {
748 /* The partial tick period already ended. Be sure the SysTick
749 * counts it only once. */
750 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
751 }
752
753 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
754 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
755 }
756 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
757
758 /* Step the tick to account for any tick periods that elapsed. */
759 vTaskStepTick( ulCompleteTickPeriods );
760
761 /* Exit with interrupts enabled. */
762 __enable_irq();
763 }
764 }
765
766 #endif /* #if configUSE_TICKLESS_IDLE */
767
768 /*-----------------------------------------------------------*/
769
770 /*
771 * Setup the SysTick timer to generate the tick interrupts at the required
772 * frequency.
773 */
774 #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
775
vPortSetupTimerInterrupt(void)776 __weak void vPortSetupTimerInterrupt( void )
777 {
778 /* Calculate the constants required to configure the tick interrupt. */
779 #if ( configUSE_TICKLESS_IDLE == 1 )
780 {
781 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
782 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
783 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
784 }
785 #endif /* configUSE_TICKLESS_IDLE */
786
787 /* Stop and clear the SysTick. */
788 portNVIC_SYSTICK_CTRL_REG = 0UL;
789 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
790
791 /* Configure SysTick to interrupt at the requested rate. */
792 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
793 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
794 }
795
796 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
797 /*-----------------------------------------------------------*/
798
vPortGetIPSR(void)799 __asm uint32_t vPortGetIPSR( void )
800 {
801 /* *INDENT-OFF* */
802 PRESERVE8
803
804 mrs r0, ipsr
805 bx r14
806 /* *INDENT-ON* */
807 }
808 /*-----------------------------------------------------------*/
809
810 #if ( configASSERT_DEFINED == 1 )
811
vPortValidateInterruptPriority(void)812 void vPortValidateInterruptPriority( void )
813 {
814 uint32_t ulCurrentInterrupt;
815 uint8_t ucCurrentPriority;
816
817 /* Obtain the number of the currently executing interrupt. */
818 ulCurrentInterrupt = vPortGetIPSR();
819
820 /* Is the interrupt number a user defined interrupt? */
821 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
822 {
823 /* Look up the interrupt's priority. */
824 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
825
826 /* The following assertion will fail if a service routine (ISR) for
827 * an interrupt that has been assigned a priority above
828 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
829 * function. ISR safe FreeRTOS API functions must *only* be called
830 * from interrupts that have been assigned a priority at or below
831 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
832 *
833 * Numerically low interrupt priority numbers represent logically high
834 * interrupt priorities, therefore the priority of the interrupt must
835 * be set to a value equal to or numerically *higher* than
836 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
837 *
838 * Interrupts that use the FreeRTOS API must not be left at their
839 * default priority of zero as that is the highest possible priority,
840 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
841 * and therefore also guaranteed to be invalid.
842 *
843 * FreeRTOS maintains separate thread and ISR API functions to ensure
844 * interrupt entry is as fast and simple as possible.
845 *
846 * The following links provide detailed information:
847 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
848 * https://www.FreeRTOS.org/FAQHelp.html */
849 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
850 }
851
852 /* Priority grouping: The interrupt controller (NVIC) allows the bits
853 * that define each interrupt's priority to be split between bits that
854 * define the interrupt's pre-emption priority bits and bits that define
855 * the interrupt's sub-priority. For simplicity all bits must be defined
856 * to be pre-emption priority bits. The following assertion will fail if
857 * this is not the case (if some bits represent a sub-priority).
858 *
859 * If the application only uses CMSIS libraries for interrupt
860 * configuration then the correct setting can be achieved on all Cortex-M
861 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
862 * scheduler. Note however that some vendor specific peripheral libraries
863 * assume a non-zero priority group setting, in which cases using a value
864 * of zero will result in unpredictable behaviour. */
865 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
866 }
867
868 #endif /* configASSERT_DEFINED */
869
