1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33 /* *INDENT-OFF* */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 /* *INDENT-ON* */
38
39 /*-----------------------------------------------------------
40 * Port specific definitions.
41 *
42 * The settings in this file configure FreeRTOS correctly for the
43 * given hardware and compiler.
44 *
45 * These settings should not be altered.
46 *-----------------------------------------------------------
47 */
48
49 /* Type definitions. */
50 #define portCHAR char
51 #define portFLOAT float
52 #define portDOUBLE double
53 #define portLONG long
54 #define portSHORT short
55 #define portSTACK_TYPE uint32_t
56 #define portBASE_TYPE long
57
58 typedef portSTACK_TYPE StackType_t;
59 typedef long BaseType_t;
60 typedef unsigned long UBaseType_t;
61
62 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
63 typedef uint16_t TickType_t;
64 #define portMAX_DELAY ( TickType_t ) 0xffff
65 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
66 typedef uint32_t TickType_t;
67 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
68
69 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
70 * not need to be guarded with a critical section. */
71 #define portTICK_TYPE_IS_ATOMIC 1
72 #else
73 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
74 #endif
75
76 /*-----------------------------------------------------------*/
77
78 /* MPU specific constants. */
79 #define portUSING_MPU_WRAPPERS 1
80 #define portPRIVILEGE_BIT ( 0x80000000UL )
81
82 #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
83 #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
84 #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
85 #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
86 #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
87 #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
88 #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
89
90 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
91 * Register (RASR). */
92 #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
93 #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
94
95 /* MPU settings that can be overriden in FreeRTOSConfig.h. */
96 #ifndef configTOTAL_MPU_REGIONS
97 /* Define to 8 for backward compatibility. */
98 #define configTOTAL_MPU_REGIONS ( 8UL )
99 #endif
100
101 /*
102 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
103 * memory type, and where necessary the cacheable and shareable properties
104 * of the memory region.
105 *
106 * The TEX, C, and B bits together indicate the memory type of the region,
107 * and:
108 * - For Normal memory, the cacheable properties of the region.
109 * - For Device memory, whether the region is shareable.
110 *
111 * For Normal memory regions, the S bit indicates whether the region is
112 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
113 *
114 * See the following two tables for setting TEX, S, C and B bits for
115 * unprivileged flash, privileged flash and privileged RAM regions.
116 *
117 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
118 | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
119 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
120 | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
121 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
122 | 000 | 0 | 1 | Device | Shared device | Shareable |
123 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
124 | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
125 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
126 | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
127 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
128 | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
129 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
130 | 001 | 0 | 1 | Reserved | Reserved | Reserved |
131 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
132 | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
133 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
134 | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
135 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
136 | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
137 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
138 | 010 | 0 | 1 | Reserved | Reserved | Reserved |
139 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
140 | 010 | 1 | X | Reserved | Reserved | Reserved |
141 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
142 | 011 | X | X | Reserved | Reserved | Reserved |
143 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
144 | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
145 | | | | | outer cacheability rules that must be exported on the | |
146 | | | | | bus. See the table below for the cacheability policy | |
147 | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
148 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
149 |
150 +-----------------------------------------+----------------------------------------+
151 | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
152 +-----------------------------------------+----------------------------------------+
153 | 00 | Non-cacheable |
154 +-----------------------------------------+----------------------------------------+
155 | 01 | Write-back, write and read allocate |
156 +-----------------------------------------+----------------------------------------+
157 | 10 | Write-through, no write allocate |
158 +-----------------------------------------+----------------------------------------+
159 | 11 | Write-back, no write allocate |
160 +-----------------------------------------+----------------------------------------+
161 */
162
163 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash
164 * region. */
165 #ifndef configTEX_S_C_B_FLASH
166 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
167 #define configTEX_S_C_B_FLASH ( 0x07UL )
168 #endif
169
170 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM
171 * region. */
172 #ifndef configTEX_S_C_B_SRAM
173 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
174 #define configTEX_S_C_B_SRAM ( 0x07UL )
175 #endif
176
177 #define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
178 #define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
179 #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
180 #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
181 #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
182 #define portFIRST_CONFIGURABLE_REGION ( 0UL )
183 #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
184 #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
185 #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
186
187 void vPortSwitchToUserMode( void );
188 #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
189
190 typedef struct MPU_REGION_REGISTERS
191 {
192 uint32_t ulRegionBaseAddress;
193 uint32_t ulRegionAttribute;
194 } xMPU_REGION_REGISTERS;
195
196 typedef struct MPU_REGION_SETTINGS
197 {
198 uint32_t ulRegionStartAddress;
199 uint32_t ulRegionEndAddress;
200 uint32_t ulRegionPermissions;
201 } xMPU_REGION_SETTINGS;
202
203 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
204
205 #ifndef configSYSTEM_CALL_STACK_SIZE
206 #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
207 #endif
208
209 typedef struct SYSTEM_CALL_STACK_INFO
210 {
211 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
212 uint32_t * pulSystemCallStack;
213 uint32_t * pulTaskStack;
214 uint32_t ulLinkRegisterAtSystemCallEntry;
215 } xSYSTEM_CALL_STACK_INFO;
216
217 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
218
219 #define MAX_CONTEXT_SIZE ( 52 )
220
221 /* Size of an Access Control List (ACL) entry in bits. */
222 #define portACL_ENTRY_SIZE_BITS ( 32U )
223
224 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
225 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
226 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
227
228 typedef struct MPU_SETTINGS
229 {
230 xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
231 xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
232 uint32_t ulContext[ MAX_CONTEXT_SIZE ];
233 uint32_t ulTaskFlags;
234
235 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
236 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
237 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
238 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
239 #endif
240 #endif
241 } xMPU_SETTINGS;
242
243 /* Architecture specifics. */
244 #define portSTACK_GROWTH ( -1 )
245 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
246 #define portBYTE_ALIGNMENT 8
247
248 /* Constants used with memory barrier intrinsics. */
249 #define portSY_FULL_READ_WRITE ( 15 )
250
251 /*-----------------------------------------------------------*/
252
253 /* SVC numbers for various services. */
254 #define portSVC_START_SCHEDULER 100
255 #define portSVC_YIELD 101
256 #define portSVC_RAISE_PRIVILEGE 102
257 #define portSVC_SYSTEM_CALL_EXIT 103
258
259 /* Scheduler utilities. */
260
261 #define portYIELD() __asm{ SVC portSVC_YIELD }
262 #define portYIELD_WITHIN_API() \
263 { \
264 /* Set a PendSV to request a context switch. */ \
265 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
266 \
267 /* Barriers are normally not required but do ensure the code is completely \
268 * within the specified behaviour for the architecture. */ \
269 __dsb( portSY_FULL_READ_WRITE ); \
270 __isb( portSY_FULL_READ_WRITE ); \
271 }
272 /*-----------------------------------------------------------*/
273
274 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
275 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
276 #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
277 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
278 /*-----------------------------------------------------------*/
279
280 /* Critical section management. */
281 extern void vPortEnterCritical( void );
282 extern void vPortExitCritical( void );
283
284 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
285 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
286 #define portENTER_CRITICAL() vPortEnterCritical()
287 #define portEXIT_CRITICAL() vPortExitCritical()
288 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
289 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
290
291 /*-----------------------------------------------------------*/
292
293 /* Architecture specific optimisations. */
294 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
295 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
296 #endif
297
298 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
299
300 /* Check the configuration. */
301 #if ( configMAX_PRIORITIES > 32 )
302 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
303 #endif
304
305 /* Store/clear the ready priorities in a bit map. */
306 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
307 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
308
309 /*-----------------------------------------------------------*/
310
311 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
312
313 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
314 /*-----------------------------------------------------------*/
315
316 /* Task function macros as described on the FreeRTOS.org WEB site. These are
317 * not necessary for to use this port. They are defined so the common demo files
318 * (which build with all the ports) will build. */
319 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
320 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
321 /*-----------------------------------------------------------*/
322
323 #ifdef configASSERT
324 void vPortValidateInterruptPriority( void );
325 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
326 #endif
327
328 /* portNOP() is not required by this port. */
329 #define portNOP()
330
331 #define portINLINE __inline
332
333 #ifndef portFORCE_INLINE
334 #define portFORCE_INLINE __forceinline
335 #endif
336 /*-----------------------------------------------------------*/
337
338 extern BaseType_t xIsPrivileged( void );
339 extern void vResetPrivilege( void );
340
341 /**
342 * @brief Checks whether or not the processor is privileged.
343 *
344 * @return 1 if the processor is already privileged, 0 otherwise.
345 */
346 #define portIS_PRIVILEGED() xIsPrivileged()
347
348 /**
349 * @brief Raise an SVC request to raise privilege.
350 */
351 #define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
352
353 /**
354 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
355 * register.
356 */
357 #define portRESET_PRIVILEGE() vResetPrivilege()
358 /*-----------------------------------------------------------*/
359
360 extern BaseType_t xPortIsTaskPrivileged( void );
361
362 /**
363 * @brief Checks whether or not the calling task is privileged.
364 *
365 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
366 */
367 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
368 /*-----------------------------------------------------------*/
369
vPortSetBASEPRI(uint32_t ulBASEPRI)370 static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
371 {
372 __asm
373 {
374 /* Barrier instructions are not used as this function is only used to
375 * lower the BASEPRI value. */
376 /* *INDENT-OFF* */
377 msr basepri, ulBASEPRI
378 /* *INDENT-ON* */
379 }
380 }
381 /*-----------------------------------------------------------*/
382
vPortRaiseBASEPRI(void)383 static portFORCE_INLINE void vPortRaiseBASEPRI( void )
384 {
385 uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
386
387 __asm
388 {
389 /* Set BASEPRI to the max syscall priority to effect a critical
390 * section. */
391 /* *INDENT-OFF* */
392 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
393 cpsid i
394 #endif
395 msr basepri, ulNewBASEPRI
396 dsb
397 isb
398 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
399 cpsie i
400 #endif
401 /* *INDENT-ON* */
402 }
403 }
404 /*-----------------------------------------------------------*/
405
vPortClearBASEPRIFromISR(void)406 static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
407 {
408 __asm
409 {
410 /* Set BASEPRI to 0 so no interrupts are masked. This function is only
411 * used to lower the mask in an interrupt, so memory barriers are not
412 * used. */
413 /* *INDENT-OFF* */
414 msr basepri, # 0
415 /* *INDENT-ON* */
416 }
417 }
418 /*-----------------------------------------------------------*/
419
ulPortRaiseBASEPRI(void)420 static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
421 {
422 uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
423
424 __asm
425 {
426 /* Set BASEPRI to the max syscall priority to effect a critical
427 * section. */
428 /* *INDENT-OFF* */
429 mrs ulReturn, basepri
430 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
431 cpsid i
432 #endif
433 msr basepri, ulNewBASEPRI
434 dsb
435 isb
436 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
437 cpsie i
438 #endif
439 /* *INDENT-ON* */
440 }
441
442 return ulReturn;
443 }
444 /*-----------------------------------------------------------*/
445
xPortIsInsideInterrupt(void)446 static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
447 {
448 uint32_t ulCurrentInterrupt;
449 BaseType_t xReturn;
450
451 /* Obtain the number of the currently executing interrupt. */
452 __asm
453 {
454 mrs ulCurrentInterrupt, ipsr
455 }
456
457 if( ulCurrentInterrupt == 0 )
458 {
459 xReturn = pdFALSE;
460 }
461 else
462 {
463 xReturn = pdTRUE;
464 }
465
466 return xReturn;
467 }
468 /*-----------------------------------------------------------*/
469
470 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
471 #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
472 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
473 #endif
474 /*-----------------------------------------------------------*/
475
476 /* *INDENT-OFF* */
477 #ifdef __cplusplus
478 }
479 #endif
480 /* *INDENT-ON* */
481
482 #endif /* PORTMACRO_H */
483
