1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4 MPU port.
31 *----------------------------------------------------------*/
32
33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
34 * all the API functions to use the MPU wrappers. That should only be done when
35 * task.h is included from an application file. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Scheduler includes. */
39 #include "FreeRTOS.h"
40 #include "task.h"
41 #include "mpu_syscall_numbers.h"
42
43 #ifndef __TARGET_FPU_VFP
44 #error This port can only be used when the project options are configured to enable hardware floating point support.
45 #endif
46
47 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
48
49 #ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
50 #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
51 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
52 #endif
53
54 /* Constants required to access and manipulate the NVIC. */
55 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
56 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
57 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
58 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
59 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
60 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
61 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
62
63 /* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
64 * that a work around is active for errata 837070. */
65 #define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
66 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
67 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
68
69 /* Constants required to access and manipulate the MPU. */
70 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
71 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
72 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
73 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
74 #define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
75 #define portMPU_ENABLE ( 0x01UL )
76 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
77 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
78 #define portMPU_REGION_VALID ( 0x10UL )
79 #define portMPU_REGION_ENABLE ( 0x01UL )
80 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
81 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
82
83 /* Constants required to access and manipulate the SysTick. */
84 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
85 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
86 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
87 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
88 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
89 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
90 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
91
92 /* Constants required to manipulate the VFP. */
93 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
94 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
95
96 /* Constants required to set up the initial stack. */
97 #define portINITIAL_XPSR ( 0x01000000UL )
98 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
99 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
100 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
101
102 /* Constants required to check the validity of an interrupt priority. */
103 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
104 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
105 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
106 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
107 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
108 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
109 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
110 #define portPRIGROUP_SHIFT ( 8UL )
111
112 /* Constants used during system call enter and exit. */
113 #define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
114 #define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
115
116 /* Offsets in the stack to the parameters when inside the SVC handler. */
117 #define portOFFSET_TO_LR ( 5 )
118 #define portOFFSET_TO_PC ( 6 )
119 #define portOFFSET_TO_PSR ( 7 )
120
121 /* For strict compliance with the Cortex-M spec the task start address should
122 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
123 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
124
125 /* Does addr lie within [start, end] address range? */
126 #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
127 ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
128
129 /* Is the access request satisfied by the available permissions? */
130 #define portIS_AUTHORIZED( accessRequest, permissions ) \
131 ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
132
133 /* Max value that fits in a uint32_t type. */
134 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
135
136 /* Check if adding a and b will result in overflow. */
137 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
138 /*-----------------------------------------------------------*/
139
140 /* Each task maintains its own interrupt status in the critical nesting
141 * variable. Note this is not saved as part of the task context as context
142 * switches can only occur when uxCriticalNesting is zero. */
143 PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
144
145 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
146
147 /*
148 * This variable is set to pdTRUE when the scheduler is started.
149 */
150 PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
151
152 #endif
153
154 /*
155 * Setup the timer to generate the tick interrupts.
156 */
157 void vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
158
159 /*
160 * Configure a number of standard MPU regions that are used by all tasks.
161 */
162 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
163
164 /*
165 * Start first task is a separate function so it can be tested in isolation.
166 */
167 static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
168
169 /*
170 * Return the smallest MPU region size that a given number of bytes will fit
171 * into. The region size is returned as the value that should be programmed
172 * into the region attribute register for that region.
173 */
174 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
175
176 /*
177 * Standard FreeRTOS exception handlers.
178 */
179 void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
180 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
181 void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
182
183 /*
184 * Starts the scheduler by restoring the context of the first task to run.
185 */
186 static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
187
188 /*
189 * C portion of the SVC handler. The SVC handler is split between an asm entry
190 * and a C wrapper for simplicity of coding and maintenance.
191 */
192 void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION;
193
194 /*
195 * Function to enable the VFP.
196 */
197 static void vPortEnableVFP( void );
198
199 /*
200 * Utility function.
201 */
202 static uint32_t prvPortGetIPSR( void );
203
204 /*
205 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
206 * FreeRTOS API functions are not called from interrupts that have been assigned
207 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
208 */
209 #if ( configASSERT_DEFINED == 1 )
210 static uint8_t ucMaxSysCallPriority = 0;
211 static uint32_t ulMaxPRIGROUPValue = 0;
212 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
213 #endif /* configASSERT_DEFINED */
214
215 /**
216 * @brief Checks whether or not the processor is privileged.
217 *
218 * @return 1 if the processor is already privileged, 0 otherwise.
219 */
220 BaseType_t xIsPrivileged( void );
221
222 /**
223 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
224 * register.
225 *
226 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
227 * Bit[0] = 0 --> The processor is running privileged
228 * Bit[0] = 1 --> The processor is running unprivileged.
229 */
230 void vResetPrivilege( void );
231
232 /**
233 * @brief Enter critical section.
234 */
235 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
236 void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
237 #else
238 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
239 #endif
240
241 /**
242 * @brief Exit from critical section.
243 */
244 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
245 void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
246 #else
247 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
248 #endif
249
250 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
251
252 /**
253 * @brief Triggers lazy stacking of FPU registers.
254 */
255 static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION;
256
257 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
258
259 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
260
261 /**
262 * @brief Sets up the system call stack so that upon returning from
263 * SVC, the system call stack is used.
264 *
265 * @param pulTaskStack The current SP when the SVC was raised.
266 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
267 * @param ucSystemCallNumber The system call number of the system call.
268 */
269 void vSystemCallEnter( uint32_t * pulTaskStack,
270 uint32_t ulLR,
271 uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
272
273 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
274
275 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
276
277 /**
278 * @brief Raise SVC for exiting from a system call.
279 */
280 void vRequestSystemCallExit( void ) PRIVILEGED_FUNCTION;
281
282 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
283
284 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
285
286 /**
287 * @brief Sets up the task stack so that upon returning from
288 * SVC, the task stack is used again.
289 *
290 * @param pulSystemCallStack The current SP when the SVC was raised.
291 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
292 */
293 void vSystemCallExit( uint32_t * pulSystemCallStack,
294 uint32_t ulLR ) PRIVILEGED_FUNCTION;
295
296 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
297
298 /**
299 * @brief Checks whether or not the calling task is privileged.
300 *
301 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
302 */
303 BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
304 /*-----------------------------------------------------------*/
305
306 /*
307 * See header file for description.
308 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters,BaseType_t xRunPrivileged,xMPU_SETTINGS * xMPUSettings)309 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
310 TaskFunction_t pxCode,
311 void * pvParameters,
312 BaseType_t xRunPrivileged,
313 xMPU_SETTINGS * xMPUSettings )
314 {
315 if( xRunPrivileged == pdTRUE )
316 {
317 xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
318 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED;
319 }
320 else
321 {
322 xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
323 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
324 }
325 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
326 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
327 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
328 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
329 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
330 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
331 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
332 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
333 xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
334
335 xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
336 xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
337 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
338 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
339 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
340 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
341 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
342 xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
343 xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
344
345 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
346 {
347 /* Ensure that the system call stack is double word aligned. */
348 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
349 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
350 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
351
352 /* This is not NULL only for the duration of a system call. */
353 xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
354 }
355 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
356
357 return &( xMPUSettings->ulContext[ 19 ] );
358 }
359 /*-----------------------------------------------------------*/
360
vSVCHandler_C(uint32_t * pulParam)361 void vSVCHandler_C( uint32_t * pulParam )
362 {
363 uint8_t ucSVCNumber;
364 uint32_t ulPC;
365
366 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
367 uint32_t ulReg;
368 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
369
370 #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
371 extern uint32_t __syscalls_flash_start__;
372 extern uint32_t __syscalls_flash_end__;
373 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
374
375 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
376 * argument (r0) is pulParam[ 0 ]. */
377 ulPC = pulParam[ portOFFSET_TO_PC ];
378 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
379
380 switch( ucSVCNumber )
381 {
382 case portSVC_START_SCHEDULER:
383 portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
384 prvRestoreContextOfFirstTask();
385 break;
386
387 case portSVC_YIELD:
388 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
389
390 /* Barriers are normally not required
391 * but do ensure the code is completely
392 * within the specified behaviour for the
393 * architecture. */
394 __asm volatile ( "dsb" );
395 __asm volatile ( "isb" );
396
397 break;
398
399 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
400 #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
401 case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
402 * svc was raised from any of the
403 * system calls. */
404
405 if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
406 ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
407 {
408 __asm
409 {
410 /* *INDENT-OFF* */
411 mrs ulReg, control /* Obtain current control value. */
412 bic ulReg, # 1 /* Set privilege bit. */
413 msr control, ulReg /* Write back new control value. */
414 /* *INDENT-ON* */
415 }
416 }
417
418 break;
419 #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
420 case portSVC_RAISE_PRIVILEGE:
421 __asm
422 {
423 /* *INDENT-OFF* */
424 mrs ulReg, control /* Obtain current control value. */
425 bic ulReg, # 1 /* Set privilege bit. */
426 msr control, ulReg /* Write back new control value. */
427 /* *INDENT-ON* */
428 }
429 break;
430 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
431 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
432
433 default: /* Unknown SVC call. */
434 break;
435 }
436 }
437 /*-----------------------------------------------------------*/
438
439 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
440
prvTriggerLazyStacking(void)441 __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */
442 {
443 /* *INDENT-OFF* */
444 PRESERVE8
445
446 vpush {s0} /* Trigger lazy stacking. */
447 vpop {s0} /* Nullify the affect of the above instruction. */
448
449 /* *INDENT-ON* */
450 }
451
452 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
453 /*-----------------------------------------------------------*/
454
455 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
456
vSystemCallEnter(uint32_t * pulTaskStack,uint32_t ulLR,uint8_t ucSystemCallNumber)457 void vSystemCallEnter( uint32_t * pulTaskStack,
458 uint32_t ulLR,
459 uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
460 {
461 extern TaskHandle_t pxCurrentTCB;
462 extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
463 xMPU_SETTINGS * pxMpuSettings;
464 uint32_t * pulSystemCallStack;
465 uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
466 extern uint32_t __syscalls_flash_start__;
467 extern uint32_t __syscalls_flash_end__;
468
469 ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
470 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
471
472 /* Checks:
473 * 1. SVC is raised from the system call section (i.e. application is
474 * not raising SVC directly).
475 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
476 * it is non-NULL only during the execution of a system call (i.e.
477 * between system call enter and exit).
478 * 3. System call is not for a kernel API disabled by the configuration
479 * in FreeRTOSConfig.h.
480 * 4. We do not need to check that ucSystemCallNumber is within range
481 * because the assembly SVC handler checks that before calling
482 * this function.
483 */
484 if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
485 ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
486 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
487 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
488 {
489 pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
490
491 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
492 {
493 /* Extended frame i.e. FPU in use. */
494 ulStackFrameSize = 26;
495 prvTriggerLazyStacking();
496 }
497 else
498 {
499 /* Standard frame i.e. FPU not in use. */
500 ulStackFrameSize = 8;
501 }
502
503 /* Make space on the system call stack for the stack frame. */
504 pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
505
506 /* Copy the stack frame. */
507 for( i = 0; i < ulStackFrameSize; i++ )
508 {
509 pulSystemCallStack[ i ] = pulTaskStack[ i ];
510 }
511
512 /* Use the pulSystemCallStack in thread mode. */
513 __asm
514 {
515 msr psp, pulSystemCallStack
516 };
517
518 /* Raise the privilege for the duration of the system call. */
519 __asm
520 {
521 mrs r1, control /* Obtain current control value. */
522 bic r1, #1 /* Clear nPRIV bit. */
523 msr control, r1 /* Write back new control value. */
524 };
525
526 /* Remember the location where we should copy the stack frame when we exit from
527 * the system call. */
528 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
529
530 /* Store the value of the Link Register before the SVC was raised.
531 * It contains the address of the caller of the System Call entry
532 * point (i.e. the caller of the MPU_<API>). We need to restore it
533 * when we exit from the system call. */
534 pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
535
536 /* Start executing the system call upon returning from this handler. */
537 pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
538
539 /* Raise a request to exit from the system call upon finishing the
540 * system call. */
541 pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
542
543 /* Record if the hardware used padding to force the stack pointer
544 * to be double word aligned. */
545 if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
546 {
547 pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
548 }
549 else
550 {
551 pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
552 }
553
554 /* We ensure in pxPortInitialiseStack that the system call stack is
555 * double word aligned and therefore, there is no need of padding.
556 * Clear the bit[9] of stacked xPSR. */
557 pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
558 }
559 }
560
561 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
562 /*-----------------------------------------------------------*/
563
564 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
565
vRequestSystemCallExit(void)566 __asm void vRequestSystemCallExit( void ) /* PRIVILEGED_FUNCTION */
567 {
568 PRESERVE8
569
570 svc #portSVC_SYSTEM_CALL_EXIT
571 }
572
573 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
574 /*-----------------------------------------------------------*/
575
576 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
577
vSystemCallExit(uint32_t * pulSystemCallStack,uint32_t ulLR)578 void vSystemCallExit( uint32_t * pulSystemCallStack,
579 uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
580 {
581 extern TaskHandle_t pxCurrentTCB;
582 xMPU_SETTINGS * pxMpuSettings;
583 uint32_t * pulTaskStack;
584 uint32_t ulStackFrameSize, ulSystemCallLocation, i, r1;
585 extern uint32_t __privileged_functions_start__;
586 extern uint32_t __privileged_functions_end__;
587
588 ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
589 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
590
591 /* Checks:
592 * 1. SVC is raised from the privileged code (i.e. application is not
593 * raising SVC directly). This SVC is only raised from
594 * vRequestSystemCallExit which is in the privileged code section.
595 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
596 * this means that we previously entered a system call and the
597 * application is not attempting to exit without entering a system
598 * call.
599 */
600 if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
601 ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
602 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
603 {
604 pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
605
606 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
607 {
608 /* Extended frame i.e. FPU in use. */
609 ulStackFrameSize = 26;
610 prvTriggerLazyStacking();
611 }
612 else
613 {
614 /* Standard frame i.e. FPU not in use. */
615 ulStackFrameSize = 8;
616 }
617
618 /* Make space on the task stack for the stack frame. */
619 pulTaskStack = pulTaskStack - ulStackFrameSize;
620
621 /* Copy the stack frame. */
622 for( i = 0; i < ulStackFrameSize; i++ )
623 {
624 pulTaskStack[ i ] = pulSystemCallStack[ i ];
625 }
626
627 /* Use the pulTaskStack in thread mode. */
628 __asm
629 {
630 msr psp, pulTaskStack
631 };
632
633 /* Drop the privilege before returning to the thread mode. */
634 __asm
635 {
636 mrs r1, control /* Obtain current control value. */
637 orr r1, #1 /* Set nPRIV bit. */
638 msr control, r1 /* Write back new control value. */
639 };
640
641 /* Return to the caller of the System Call entry point (i.e. the
642 * caller of the MPU_<API>). */
643 pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
644 /* Ensure that LR has a valid value.*/
645 pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
646
647 /* If the hardware used padding to force the stack pointer
648 * to be double word aligned, set the stacked xPSR bit[9],
649 * otherwise clear it. */
650 if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
651 {
652 pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
653 }
654 else
655 {
656 pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
657 }
658
659 /* This is not NULL only for the duration of the system call. */
660 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
661 }
662 }
663
664 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
665 /*-----------------------------------------------------------*/
666
xPortIsTaskPrivileged(void)667 BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
668 {
669 BaseType_t xTaskIsPrivileged = pdFALSE;
670 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
671
672 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
673 {
674 xTaskIsPrivileged = pdTRUE;
675 }
676
677 return xTaskIsPrivileged;
678 }
679 /*-----------------------------------------------------------*/
680
681 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
682
683 /* *INDENT-OFF* */
vPortSVCHandler(void)684 __asm void vPortSVCHandler( void )
685 {
686 extern vSVCHandler_C
687 extern vSystemCallEnter
688 extern vSystemCallExit
689
690 PRESERVE8
691
692 tst lr, #4
693 ite eq
694 mrseq r0, msp
695 mrsne r0, psp
696
697 ldr r1, [r0, #24]
698 ldrb r2, [r1, #-2]
699 cmp r2, #NUM_SYSTEM_CALLS
700 blt syscall_enter
701 cmp r2, #portSVC_SYSTEM_CALL_EXIT
702 beq syscall_exit
703 b vSVCHandler_C
704
705 syscall_enter
706 mov r1, lr
707 b vSystemCallEnter
708
709 syscall_exit
710 mov r1, lr
711 b vSystemCallExit
712 }
713
714 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
715
vPortSVCHandler(void)716 __asm void vPortSVCHandler( void )
717 {
718 extern vSVCHandler_C
719
720 PRESERVE8
721
722 /* Assumes psp was in use. */
723 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
724 tst lr, # 4
725 ite eq
726 mrseq r0, msp
727 mrsne r0, psp
728 #else
729 mrs r0, psp
730 #endif
731
732 b vSVCHandler_C
733 }
734 /* *INDENT-ON* */
735
736 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
737 /*-----------------------------------------------------------*/
738
prvRestoreContextOfFirstTask(void)739 __asm void prvRestoreContextOfFirstTask( void )
740 {
741 /* *INDENT-OFF* */
742 PRESERVE8
743
744 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
745 ldr r0, [r0]
746 ldr r0, [r0]
747 msr msp, r0 /* Set the msp back to the start of the stack. */
748
749 /*------------ Program MPU. ------------ */
750 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
751 ldr r2, [r3] /* r2 = pxCurrentTCB. */
752 add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
753
754 dmb /* Complete outstanding transfers before disabling MPU. */
755 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
756 ldr r3, [r0] /* Read the value of MPU_CTRL. */
757 bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
758 str r3, [r0] /* Disable MPU. */
759
760 ldr r0, =0xe000ed9c /* Region Base Address register. */
761 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
762 stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
763
764 #if ( configTOTAL_MPU_REGIONS == 16 )
765 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
766 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
767 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
768 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
769 #endif /* configTOTAL_MPU_REGIONS == 16. */
770
771 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
772 ldr r3, [r0] /* Read the value of MPU_CTRL. */
773 orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
774 str r3, [r0] /* Enable MPU. */
775 dsb /* Force memory writes before continuing. */
776
777 /*---------- Restore Context. ---------- */
778 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
779 ldr r2, [r3] /* r2 = pxCurrentTCB. */
780 ldr r1, [r2] /* r1 = Location of saved context in TCB. */
781
782 ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
783 msr psp, r0
784 stmia r0, {r4-r11} /* Copy the hardware saved context on the task stack. */
785 ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
786 msr control, r3
787 str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
788
789 mov r0, #0
790 msr basepri, r0
791 bx lr
792 /* *INDENT-ON* */
793 }
794 /*-----------------------------------------------------------*/
795
796 /*
797 * See header file for description.
798 */
xPortStartScheduler(void)799 BaseType_t xPortStartScheduler( void )
800 {
801 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
802 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
803 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
804
805 /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
806 * and r0p1 cores. */
807 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
808 configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
809 #else
810 /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
811 * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
812 * FreeRTOSConfig.h. */
813 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
814 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
815 #endif
816
817 #if ( configASSERT_DEFINED == 1 )
818 {
819 volatile uint8_t ucOriginalPriority;
820 volatile uint32_t ulImplementedPrioBits = 0;
821 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
822 volatile uint8_t ucMaxPriorityValue;
823
824 /* Determine the maximum priority from which ISR safe FreeRTOS API
825 * functions can be called. ISR safe functions are those that end in
826 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
827 * ensure interrupt entry is as fast and simple as possible.
828 *
829 * Save the interrupt priority value that is about to be clobbered. */
830 ucOriginalPriority = *pucFirstUserPriorityRegister;
831
832 /* Determine the number of priority bits available. First write to all
833 * possible bits. */
834 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
835
836 /* Read the value back to see how many bits stuck. */
837 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
838
839 /* Use the same mask on the maximum system call priority. */
840 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
841
842 /* Check that the maximum system call priority is nonzero after
843 * accounting for the number of priority bits supported by the
844 * hardware. A priority of 0 is invalid because setting the BASEPRI
845 * register to 0 unmasks all interrupts, and interrupts with priority 0
846 * cannot be masked using BASEPRI.
847 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
848 configASSERT( ucMaxSysCallPriority );
849
850 /* Check that the bits not implemented in hardware are zero in
851 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
852 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
853
854 /* Calculate the maximum acceptable priority group value for the number
855 * of bits read back. */
856
857 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
858 {
859 ulImplementedPrioBits++;
860 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
861 }
862
863 if( ulImplementedPrioBits == 8 )
864 {
865 /* When the hardware implements 8 priority bits, there is no way for
866 * the software to configure PRIGROUP to not have sub-priorities. As
867 * a result, the least significant bit is always used for sub-priority
868 * and there are 128 preemption priorities and 2 sub-priorities.
869 *
870 * This may cause some confusion in some cases - for example, if
871 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
872 * priority interrupts will be masked in Critical Sections as those
873 * are at the same preemption priority. This may appear confusing as
874 * 4 is higher (numerically lower) priority than
875 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
876 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
877 * to 4, this confusion does not happen and the behaviour remains the same.
878 *
879 * The following assert ensures that the sub-priority bit in the
880 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
881 * confusion. */
882 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
883 ulMaxPRIGROUPValue = 0;
884 }
885 else
886 {
887 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
888 }
889
890 /* Shift the priority group value back to its position within the AIRCR
891 * register. */
892 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
893 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
894
895 /* Restore the clobbered interrupt priority register to its original
896 * value. */
897 *pucFirstUserPriorityRegister = ucOriginalPriority;
898 }
899 #endif /* configASSERT_DEFINED */
900
901 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
902 * handler higher priority so it can be used to exit a critical section (where
903 * lower priorities are masked). */
904 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
905 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
906
907 /* Configure the regions in the MPU that are common to all tasks. */
908 prvSetupMPU();
909
910 /* Start the timer that generates the tick ISR. Interrupts are disabled
911 * here already. */
912 vSetupTimerInterrupt();
913
914 /* Initialise the critical nesting count ready for the first task. */
915 uxCriticalNesting = 0;
916
917 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
918 {
919 xSchedulerRunning = pdTRUE;
920 }
921 #endif
922
923 /* Ensure the VFP is enabled - it should be anyway. */
924 vPortEnableVFP();
925
926 /* Lazy save always. */
927 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
928
929 /* Start the first task. */
930 prvStartFirstTask();
931
932 /* Should not get here! */
933 return 0;
934 }
935 /*-----------------------------------------------------------*/
936
prvStartFirstTask(void)937 __asm void prvStartFirstTask( void )
938 {
939 /* *INDENT-OFF* */
940 PRESERVE8
941
942 /* Use the NVIC offset register to locate the stack. */
943 ldr r0, =0xE000ED08
944 ldr r0, [ r0 ]
945 ldr r0, [ r0 ]
946 /* Set the msp back to the start of the stack. */
947 msr msp, r0
948
949 /* Clear the bit that indicates the FPU is in use in case the FPU was used
950 * before the scheduler was started - which would otherwise result in the
951 * unnecessary leaving of space in the SVC stack for lazy saving of FPU
952 * registers. */
953 mov r0, #0
954 msr control, r0
955 /* Globally enable interrupts. */
956 cpsie i
957 cpsie f
958 dsb
959 isb
960 svc portSVC_START_SCHEDULER /* System call to start first task. */
961 nop
962 nop
963 /* *INDENT-ON* */
964 }
965
vPortEndScheduler(void)966 void vPortEndScheduler( void )
967 {
968 /* Not implemented in ports where there is nothing to return to.
969 * Artificially force an assert. */
970 configASSERT( uxCriticalNesting == 1000UL );
971 }
972 /*-----------------------------------------------------------*/
973
vPortEnterCritical(void)974 void vPortEnterCritical( void )
975 {
976 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
977 if( portIS_PRIVILEGED() == pdFALSE )
978 {
979 portRAISE_PRIVILEGE();
980 portMEMORY_BARRIER();
981
982 portDISABLE_INTERRUPTS();
983 uxCriticalNesting++;
984 portMEMORY_BARRIER();
985
986 portRESET_PRIVILEGE();
987 portMEMORY_BARRIER();
988 }
989 else
990 {
991 portDISABLE_INTERRUPTS();
992 uxCriticalNesting++;
993 }
994 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
995 portDISABLE_INTERRUPTS();
996 uxCriticalNesting++;
997 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
998 }
999 /*-----------------------------------------------------------*/
1000
vPortExitCritical(void)1001 void vPortExitCritical( void )
1002 {
1003 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
1004 if( portIS_PRIVILEGED() == pdFALSE )
1005 {
1006 portRAISE_PRIVILEGE();
1007 portMEMORY_BARRIER();
1008
1009 configASSERT( uxCriticalNesting );
1010 uxCriticalNesting--;
1011
1012 if( uxCriticalNesting == 0 )
1013 {
1014 portENABLE_INTERRUPTS();
1015 }
1016
1017 portMEMORY_BARRIER();
1018
1019 portRESET_PRIVILEGE();
1020 portMEMORY_BARRIER();
1021 }
1022 else
1023 {
1024 configASSERT( uxCriticalNesting );
1025 uxCriticalNesting--;
1026
1027 if( uxCriticalNesting == 0 )
1028 {
1029 portENABLE_INTERRUPTS();
1030 }
1031 }
1032 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1033 configASSERT( uxCriticalNesting );
1034 uxCriticalNesting--;
1035
1036 if( uxCriticalNesting == 0 )
1037 {
1038 portENABLE_INTERRUPTS();
1039 }
1040 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1041 }
1042 /*-----------------------------------------------------------*/
1043
xPortPendSVHandler(void)1044 __asm void xPortPendSVHandler( void )
1045 {
1046 extern uxCriticalNesting;
1047 extern pxCurrentTCB;
1048 extern vTaskSwitchContext;
1049
1050 /* *INDENT-OFF* */
1051 PRESERVE8
1052
1053 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
1054 ldr r2, [r3] /* r2 = pxCurrentTCB. */
1055 ldr r1, [r2] /* r1 = Location where the context should be saved. */
1056
1057 /*------------ Save Context. ----------- */
1058 mrs r3, control
1059 mrs r0, psp
1060 isb
1061
1062 add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */
1063 tst lr, #0x10
1064 ittt eq
1065 vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
1066 vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
1067 vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
1068 sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */
1069
1070 stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */
1071 ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */
1072 stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */
1073 str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */
1074
1075 /*---------- Select next task. --------- */
1076 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
1077 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1078 cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1079 #endif
1080 msr basepri, r0
1081 dsb
1082 isb
1083 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1084 cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1085 #endif
1086 bl vTaskSwitchContext
1087 mov r0, #0
1088 msr basepri, r0
1089
1090 /*------------ Program MPU. ------------ */
1091 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
1092 ldr r2, [r3] /* r2 = pxCurrentTCB. */
1093 add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
1094
1095 dmb /* Complete outstanding transfers before disabling MPU. */
1096 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
1097 ldr r3, [r0] /* Read the value of MPU_CTRL. */
1098 bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
1099 str r3, [r0] /* Disable MPU. */
1100
1101 ldr r0, =0xe000ed9c /* Region Base Address register. */
1102 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
1103 stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
1104
1105 #if ( configTOTAL_MPU_REGIONS == 16 )
1106 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
1107 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
1108 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
1109 stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
1110 #endif /* configTOTAL_MPU_REGIONS == 16. */
1111
1112 ldr r0, =0xe000ed94 /* MPU_CTRL register. */
1113 ldr r3, [r0] /* Read the value of MPU_CTRL. */
1114 orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
1115 str r3, [r0] /* Enable MPU. */
1116 dsb /* Force memory writes before continuing. */
1117
1118 /*---------- Restore Context. ---------- */
1119 ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */
1120 ldr r2, [r3] /* r2 = pxCurrentTCB. */
1121 ldr r1, [r2] /* r1 = Location of saved context in TCB. */
1122
1123 ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
1124 msr psp, r0
1125 stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */
1126 ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
1127 msr control, r3
1128
1129 tst lr, #0x10
1130 ittt eq
1131 vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
1132 vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
1133 vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
1134
1135 str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
1136 bx lr
1137 /* *INDENT-ON* */
1138 }
1139 /*-----------------------------------------------------------*/
1140
xPortSysTickHandler(void)1141 void xPortSysTickHandler( void )
1142 {
1143 uint32_t ulDummy;
1144
1145 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
1146 {
1147 /* Increment the RTOS tick. */
1148 if( xTaskIncrementTick() != pdFALSE )
1149 {
1150 /* Pend a context switch. */
1151 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
1152 }
1153 }
1154 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
1155 }
1156 /*-----------------------------------------------------------*/
1157
1158 /*
1159 * Setup the systick timer to generate the tick interrupts at the required
1160 * frequency.
1161 */
vSetupTimerInterrupt(void)1162 __weak void vSetupTimerInterrupt( void )
1163 {
1164 /* Reset the SysTick. */
1165 portNVIC_SYSTICK_CTRL_REG = 0UL;
1166 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
1167
1168 /* Configure SysTick to interrupt at the requested rate. */
1169 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
1170 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
1171 }
1172 /*-----------------------------------------------------------*/
1173
vPortSwitchToUserMode(void)1174 __asm void vPortSwitchToUserMode( void )
1175 {
1176 /* *INDENT-OFF* */
1177 PRESERVE8
1178
1179 mrs r0, control
1180 orr r0, #1
1181 msr control, r0
1182 bx r14
1183 /* *INDENT-ON* */
1184 }
1185 /*-----------------------------------------------------------*/
1186
vPortEnableVFP(void)1187 __asm void vPortEnableVFP( void )
1188 {
1189 /* *INDENT-OFF* */
1190 PRESERVE8
1191
1192 ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
1193 ldr r1, [ r0 ]
1194
1195 orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
1196 str r1, [ r0 ]
1197 bx r14
1198 /* *INDENT-ON* */
1199 }
1200 /*-----------------------------------------------------------*/
1201
prvSetupMPU(void)1202 static void prvSetupMPU( void )
1203 {
1204 extern uint32_t __privileged_functions_start__;
1205 extern uint32_t __privileged_functions_end__;
1206 extern uint32_t __FLASH_segment_start__;
1207 extern uint32_t __FLASH_segment_end__;
1208 extern uint32_t __privileged_data_start__;
1209 extern uint32_t __privileged_data_end__;
1210
1211 /* The only permitted number of regions are 8 or 16. */
1212 configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
1213
1214 /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
1215 configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
1216
1217 /* Check the expected MPU is present. */
1218 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
1219 {
1220 /* First setup the unprivileged flash for unprivileged read only access. */
1221 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
1222 ( portMPU_REGION_VALID ) |
1223 ( portUNPRIVILEGED_FLASH_REGION );
1224
1225 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
1226 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1227 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
1228 ( portMPU_REGION_ENABLE );
1229
1230 /* Setup the privileged flash for privileged only access. This is where
1231 * the kernel code is placed. */
1232 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
1233 ( portMPU_REGION_VALID ) |
1234 ( portPRIVILEGED_FLASH_REGION );
1235
1236 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
1237 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1238 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
1239 ( portMPU_REGION_ENABLE );
1240
1241 /* Setup the privileged data RAM region. This is where the kernel data
1242 * is placed. */
1243 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
1244 ( portMPU_REGION_VALID ) |
1245 ( portPRIVILEGED_RAM_REGION );
1246
1247 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
1248 ( portMPU_REGION_EXECUTE_NEVER ) |
1249 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1250 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
1251 ( portMPU_REGION_ENABLE );
1252
1253 /* By default allow everything to access the general peripherals. The
1254 * system peripherals and registers are protected. */
1255 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
1256 ( portMPU_REGION_VALID ) |
1257 ( portGENERAL_PERIPHERALS_REGION );
1258
1259 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
1260 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
1261 ( portMPU_REGION_ENABLE );
1262
1263 /* Enable the memory fault exception. */
1264 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
1265
1266 /* Enable the MPU with the background region configured. */
1267 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
1268 }
1269 }
1270 /*-----------------------------------------------------------*/
1271
prvGetMPURegionSizeSetting(uint32_t ulActualSizeInBytes)1272 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
1273 {
1274 uint32_t ulRegionSize, ulReturnValue = 4;
1275
1276 /* 32 is the smallest region size, 31 is the largest valid value for
1277 * ulReturnValue. */
1278 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
1279 {
1280 if( ulActualSizeInBytes <= ulRegionSize )
1281 {
1282 break;
1283 }
1284 else
1285 {
1286 ulReturnValue++;
1287 }
1288 }
1289
1290 /* Shift the code by one before returning so it can be written directly
1291 * into the the correct bit position of the attribute register. */
1292 return( ulReturnValue << 1UL );
1293 }
1294 /*-----------------------------------------------------------*/
1295
xIsPrivileged(void)1296 __asm BaseType_t xIsPrivileged( void )
1297 {
1298 /* *INDENT-OFF* */
1299 PRESERVE8
1300
1301 mrs r0, control /* r0 = CONTROL. */
1302 tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
1303 ite ne
1304 movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
1305 moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
1306 bx lr /* Return. */
1307 /* *INDENT-ON* */
1308 }
1309 /*-----------------------------------------------------------*/
1310
vResetPrivilege(void)1311 __asm void vResetPrivilege( void )
1312 {
1313 /* *INDENT-OFF* */
1314 PRESERVE8
1315
1316 mrs r0, control /* r0 = CONTROL. */
1317 orrs r0, #1 /* r0 = r0 | 1. */
1318 msr control, r0 /* CONTROL = r0. */
1319 bx lr /* Return. */
1320 /* *INDENT-ON* */
1321 }
1322 /*-----------------------------------------------------------*/
1323
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,uint32_t ulStackDepth)1324 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
1325 const struct xMEMORY_REGION * const xRegions,
1326 StackType_t * pxBottomOfStack,
1327 uint32_t ulStackDepth )
1328 {
1329 extern uint32_t __SRAM_segment_start__;
1330 extern uint32_t __SRAM_segment_end__;
1331 extern uint32_t __privileged_data_start__;
1332 extern uint32_t __privileged_data_end__;
1333
1334
1335 int32_t lIndex;
1336 uint32_t ul;
1337
1338 if( xRegions == NULL )
1339 {
1340 /* No MPU regions are specified so allow access to all RAM. */
1341 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1342 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
1343 ( portMPU_REGION_VALID ) |
1344 ( portSTACK_REGION ); /* Region number. */
1345
1346 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1347 ( portMPU_REGION_READ_WRITE ) |
1348 ( portMPU_REGION_EXECUTE_NEVER ) |
1349 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1350 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
1351 ( portMPU_REGION_ENABLE );
1352
1353 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
1354 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
1355 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1356 tskMPU_WRITE_PERMISSION );
1357
1358 /* Invalidate user configurable regions. */
1359 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1360 {
1361 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1362 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1363 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1364 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1365 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1366 }
1367 }
1368 else
1369 {
1370 /* This function is called automatically when the task is created - in
1371 * which case the stack region parameters will be valid. At all other
1372 * times the stack parameters will not be valid and it is assumed that the
1373 * stack region has already been configured. */
1374 if( ulStackDepth > 0 )
1375 {
1376 /* Define the region that allows access to the stack. */
1377 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1378 ( ( uint32_t ) pxBottomOfStack ) |
1379 ( portMPU_REGION_VALID ) |
1380 ( portSTACK_REGION ); /* Region number. */
1381
1382 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1383 ( portMPU_REGION_READ_WRITE ) |
1384 ( portMPU_REGION_EXECUTE_NEVER ) |
1385 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
1386 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1387 ( portMPU_REGION_ENABLE );
1388
1389 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
1390 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
1391 ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
1392 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1393 tskMPU_WRITE_PERMISSION );
1394 }
1395
1396 lIndex = 0;
1397
1398 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1399 {
1400 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
1401 {
1402 /* Translate the generic region definition contained in
1403 * xRegions into the CM4 specific MPU settings that are then
1404 * stored in xMPUSettings. */
1405 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
1406 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
1407 ( portMPU_REGION_VALID ) |
1408 ( ul - 1UL ); /* Region number. */
1409
1410 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
1411 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
1412 ( xRegions[ lIndex ].ulParameters ) |
1413 ( portMPU_REGION_ENABLE );
1414
1415 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
1416 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
1417 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1418
1419 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
1420 ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
1421 {
1422 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
1423 }
1424
1425 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
1426 {
1427 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
1428 }
1429 }
1430 else
1431 {
1432 /* Invalidate the region. */
1433 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1434 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1435 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1436 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1437 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1438 }
1439
1440 lIndex++;
1441 }
1442 }
1443 }
1444 /*-----------------------------------------------------------*/
1445
xPortIsAuthorizedToAccessBuffer(const void * pvBuffer,uint32_t ulBufferLength,uint32_t ulAccessRequested)1446 BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
1447 uint32_t ulBufferLength,
1448 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
1449
1450 {
1451 uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
1452 BaseType_t xAccessGranted = pdFALSE;
1453 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1454
1455 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1456 {
1457 xAccessGranted = pdTRUE;
1458 }
1459 else
1460 {
1461 if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
1462 {
1463 ulBufferStartAddress = ( uint32_t ) pvBuffer;
1464 ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
1465
1466 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
1467 {
1468 if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
1469 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1470 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1471 portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
1472 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1473 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1474 portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
1475 {
1476 xAccessGranted = pdTRUE;
1477 break;
1478 }
1479 }
1480 }
1481 }
1482
1483 return xAccessGranted;
1484 }
1485 /*-----------------------------------------------------------*/
1486
prvPortGetIPSR(void)1487 __asm uint32_t prvPortGetIPSR( void )
1488 {
1489 /* *INDENT-OFF* */
1490 PRESERVE8
1491
1492 mrs r0, ipsr
1493 bx r14
1494 /* *INDENT-ON* */
1495 }
1496 /*-----------------------------------------------------------*/
1497
1498 #if ( configASSERT_DEFINED == 1 )
1499
vPortValidateInterruptPriority(void)1500 void vPortValidateInterruptPriority( void )
1501 {
1502 uint32_t ulCurrentInterrupt;
1503 uint8_t ucCurrentPriority;
1504
1505 /* Obtain the number of the currently executing interrupt. */
1506 ulCurrentInterrupt = prvPortGetIPSR();
1507
1508 /* Is the interrupt number a user defined interrupt? */
1509 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
1510 {
1511 /* Look up the interrupt's priority. */
1512 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
1513
1514 /* The following assertion will fail if a service routine (ISR) for
1515 * an interrupt that has been assigned a priority above
1516 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
1517 * function. ISR safe FreeRTOS API functions must *only* be called
1518 * from interrupts that have been assigned a priority at or below
1519 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1520 *
1521 * Numerically low interrupt priority numbers represent logically high
1522 * interrupt priorities, therefore the priority of the interrupt must
1523 * be set to a value equal to or numerically *higher* than
1524 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1525 *
1526 * Interrupts that use the FreeRTOS API must not be left at their
1527 * default priority of zero as that is the highest possible priority,
1528 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
1529 * and therefore also guaranteed to be invalid.
1530 *
1531 * FreeRTOS maintains separate thread and ISR API functions to ensure
1532 * interrupt entry is as fast and simple as possible.
1533 *
1534 * The following links provide detailed information:
1535 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
1536 * https://www.FreeRTOS.org/FAQHelp.html */
1537 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
1538 }
1539
1540 /* Priority grouping: The interrupt controller (NVIC) allows the bits
1541 * that define each interrupt's priority to be split between bits that
1542 * define the interrupt's pre-emption priority bits and bits that define
1543 * the interrupt's sub-priority. For simplicity all bits must be defined
1544 * to be pre-emption priority bits. The following assertion will fail if
1545 * this is not the case (if some bits represent a sub-priority).
1546 *
1547 * If the application only uses CMSIS libraries for interrupt
1548 * configuration then the correct setting can be achieved on all Cortex-M
1549 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
1550 * scheduler. Note however that some vendor specific peripheral libraries
1551 * assume a non-zero priority group setting, in which cases using a value
1552 * of zero will result in unpredictable behaviour. */
1553 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
1554 }
1555
1556 #endif /* configASSERT_DEFINED */
1557 /*-----------------------------------------------------------*/
1558
1559 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1560
vPortGrantAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1561 void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1562 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1563 {
1564 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1565 xMPU_SETTINGS * xTaskMpuSettings;
1566
1567 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1568 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1569
1570 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1571
1572 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
1573 }
1574
1575 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1576 /*-----------------------------------------------------------*/
1577
1578 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1579
vPortRevokeAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1580 void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1581 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1582 {
1583 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1584 xMPU_SETTINGS * xTaskMpuSettings;
1585
1586 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1587 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1588
1589 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1590
1591 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
1592 }
1593
1594 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1595 /*-----------------------------------------------------------*/
1596
1597 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1598
1599 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
1600
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1601 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1602 {
1603 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1604 BaseType_t xAccessGranted = pdFALSE;
1605 const xMPU_SETTINGS * xTaskMpuSettings;
1606
1607 if( xSchedulerRunning == pdFALSE )
1608 {
1609 /* Grant access to all the kernel objects before the scheduler
1610 * is started. It is necessary because there is no task running
1611 * yet and therefore, we cannot use the permissions of any
1612 * task. */
1613 xAccessGranted = pdTRUE;
1614 }
1615 else
1616 {
1617 xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1618
1619 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1620 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1621
1622 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1623 {
1624 xAccessGranted = pdTRUE;
1625 }
1626 else
1627 {
1628 if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
1629 {
1630 xAccessGranted = pdTRUE;
1631 }
1632 }
1633 }
1634
1635 return xAccessGranted;
1636 }
1637
1638 #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1639
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1640 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1641 {
1642 ( void ) lInternalIndexOfKernelObject;
1643
1644 /* If Access Control List feature is not used, all the tasks have
1645 * access to all the kernel objects. */
1646 return pdTRUE;
1647 }
1648
1649 #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1650
1651 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1652 /*-----------------------------------------------------------*/
1653
