1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31
32 /* Scheduler includes. */
33 #include "FreeRTOS.h"
34 #include "task.h"
35
36 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
37 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
38 #endif
39
40 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
41 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
42 #endif
43
44 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
45 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
46 #endif
47
48 #ifndef configSETUP_TICK_INTERRUPT
49 #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
50 #endif /* configSETUP_TICK_INTERRUPT */
51
52 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
53 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
54 #endif
55
56 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
57 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
58 #endif
59
60 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
61 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
62 #endif
63
64 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
65 /* Check the configuration. */
66 #if( configMAX_PRIORITIES > 32 )
67 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
68 #endif
69 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
70
71 /* In case security extensions are implemented. */
72 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
73 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
74 #endif
75
76 #ifndef configCLEAR_TICK_INTERRUPT
77 #define configCLEAR_TICK_INTERRUPT()
78 #endif
79
80 /* The number of bits to shift for an interrupt priority is dependent on the
81 number of bits implemented by the interrupt controller. */
82 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
83 #define portPRIORITY_SHIFT 4
84 #define portMAX_BINARY_POINT_VALUE 3
85 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
86 #define portPRIORITY_SHIFT 3
87 #define portMAX_BINARY_POINT_VALUE 2
88 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
89 #define portPRIORITY_SHIFT 2
90 #define portMAX_BINARY_POINT_VALUE 1
91 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
92 #define portPRIORITY_SHIFT 1
93 #define portMAX_BINARY_POINT_VALUE 0
94 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
95 #define portPRIORITY_SHIFT 0
96 #define portMAX_BINARY_POINT_VALUE 0
97 #else
98 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
99 #endif
100
101 /* A critical section is exited when the critical section nesting count reaches
102 this value. */
103 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
104
105 /* In all GICs 255 can be written to the priority mask register to unmask all
106 (but the lowest) interrupt priority. */
107 #define portUNMASK_VALUE ( 0xFFUL )
108
109 /* Tasks are not created with a floating point context, but can be given a
110 floating point context after they have been created. A variable is stored as
111 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
112 does not have an FPU context, or any other value if the task does have an FPU
113 context. */
114 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
115
116 /* Interrupt controller access addresses. */
117 #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
118 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
119 #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
120 #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
121 #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
122 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
123 #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
124 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
125 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
126 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
127 #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
128 #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
129
130 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
131 point is zero. */
132 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
133
134 /* Constants required to setup the initial task context. */
135 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
136 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
137 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
138
139 /* Masks all bits in the APSR other than the mode bits. */
140 #define portAPSR_MODE_BITS_MASK ( 0x1F )
141
142 /* The value of the mode bits in the APSR when the CPU is executing in user
143 mode. */
144 #define portAPSR_USER_MODE ( 0x10 )
145
146 /* Macro to unmask all interrupt priorities. */
147 #define portCLEAR_INTERRUPT_MASK() \
148 { \
149 __disable_irq(); \
150 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
151 __asm( "DSB \n" \
152 "ISB \n" ); \
153 __enable_irq(); \
154 }
155
156 /*-----------------------------------------------------------*/
157
158 /*
159 * Starts the first task executing. This function is necessarily written in
160 * assembly code so is implemented in portASM.s.
161 */
162 extern void vPortRestoreTaskContext( void );
163
164 /*
165 * Used to catch tasks that attempt to return from their implementing function.
166 */
167 static void prvTaskExitError( void );
168
169 /*-----------------------------------------------------------*/
170
171 /* A variable is used to keep track of the critical section nesting. This
172 variable has to be stored as part of the task context and must be initialised to
173 a non zero value to ensure interrupts don't inadvertently become unmasked before
174 the scheduler starts. As it is stored as part of the task context it will
175 automatically be set to 0 when the first task is started. */
176 volatile uint32_t ulCriticalNesting = 9999UL;
177
178 /* Used to pass constants into the ASM code. The address at which variables are
179 placed is the constant value so indirect loads in the asm code are not
180 required. */
181 uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
182 uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
183 uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
184 uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
185
186 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
187 a floating point context must be saved and restored for the task. */
188 uint32_t ulPortTaskHasFPUContext = pdFALSE;
189
190 /* Set to 1 to pend a context switch from an ISR. */
191 uint32_t ulPortYieldRequired = pdFALSE;
192
193 /* Counts the interrupt nesting depth. A context switch is only performed if
194 if the nesting depth is 0. */
195 uint32_t ulPortInterruptNesting = 0UL;
196
197 /*-----------------------------------------------------------*/
198
199 /*
200 * See header file for description.
201 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)202 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
203 {
204 /* Setup the initial stack of the task. The stack is set exactly as
205 expected by the portRESTORE_CONTEXT() macro.
206
207 The fist real value on the stack is the status register, which is set for
208 system mode, with interrupts enabled. A few NULLs are added first to ensure
209 GDB does not try decoding a non-existent return address. */
210 *pxTopOfStack = NULL;
211 pxTopOfStack--;
212 *pxTopOfStack = NULL;
213 pxTopOfStack--;
214 *pxTopOfStack = NULL;
215 pxTopOfStack--;
216 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
217
218 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
219 {
220 /* The task will start in THUMB mode. */
221 *pxTopOfStack |= portTHUMB_MODE_BIT;
222 }
223
224 pxTopOfStack--;
225
226 /* Next the return address, which in this case is the start of the task. */
227 *pxTopOfStack = ( StackType_t ) pxCode;
228 pxTopOfStack--;
229
230 /* Next all the registers other than the stack pointer. */
231 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
232 pxTopOfStack--;
233 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
234 pxTopOfStack--;
235 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
236 pxTopOfStack--;
237 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
238 pxTopOfStack--;
239 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
240 pxTopOfStack--;
241 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
242 pxTopOfStack--;
243 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
244 pxTopOfStack--;
245 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
246 pxTopOfStack--;
247 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
248 pxTopOfStack--;
249 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
250 pxTopOfStack--;
251 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
252 pxTopOfStack--;
253 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
254 pxTopOfStack--;
255 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
256 pxTopOfStack--;
257 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
258 pxTopOfStack--;
259
260 /* The task will start with a critical nesting count of 0 as interrupts are
261 enabled. */
262 *pxTopOfStack = portNO_CRITICAL_NESTING;
263 pxTopOfStack--;
264
265 /* The task will start without a floating point context. A task that uses
266 the floating point hardware must call vPortTaskUsesFPU() before executing
267 any floating point instructions. */
268 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
269
270 return pxTopOfStack;
271 }
272 /*-----------------------------------------------------------*/
273
prvTaskExitError(void)274 static void prvTaskExitError( void )
275 {
276 /* A function that implements a task must not exit or attempt to return to
277 its caller as there is nothing to return to. If a task wants to exit it
278 should instead call vTaskDelete( NULL ).
279
280 Artificially force an assert() to be triggered if configASSERT() is
281 defined, then stop here so application writers can catch the error. */
282 configASSERT( ulPortInterruptNesting == ~0UL );
283 portDISABLE_INTERRUPTS();
284 for( ;; );
285 }
286 /*-----------------------------------------------------------*/
287
xPortStartScheduler(void)288 BaseType_t xPortStartScheduler( void )
289 {
290 uint32_t ulAPSR;
291
292 /* Only continue if the CPU is not in User mode. The CPU must be in a
293 Privileged mode for the scheduler to start. */
294 __asm( "MRS ulAPSR, APSR" );
295 ulAPSR &= portAPSR_MODE_BITS_MASK;
296 configASSERT( ulAPSR != portAPSR_USER_MODE );
297
298 if( ulAPSR != portAPSR_USER_MODE )
299 {
300 /* Only continue if the binary point value is set to its lowest possible
301 setting. See the comments in vPortValidateInterruptPriority() below for
302 more information. */
303 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
304
305 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
306 {
307 /* Start the timer that generates the tick ISR. */
308 configSETUP_TICK_INTERRUPT();
309
310 __enable_irq();
311 vPortRestoreTaskContext();
312 }
313 }
314
315 /* Will only get here if vTaskStartScheduler() was called with the CPU in
316 a non-privileged mode or the binary point register was not set to its lowest
317 possible value. */
318 return 0;
319 }
320 /*-----------------------------------------------------------*/
321
vPortEndScheduler(void)322 void vPortEndScheduler( void )
323 {
324 /* Not implemented in ports where there is nothing to return to.
325 Artificially force an assert. */
326 configASSERT( ulCriticalNesting == 1000UL );
327 }
328 /*-----------------------------------------------------------*/
329
vPortEnterCritical(void)330 void vPortEnterCritical( void )
331 {
332 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
333 ulPortSetInterruptMask();
334
335 /* Now interrupts are disabled ulCriticalNesting can be accessed
336 directly. Increment ulCriticalNesting to keep a count of how many times
337 portENTER_CRITICAL() has been called. */
338 ulCriticalNesting++;
339
340 /* This is not the interrupt safe version of the enter critical function so
341 assert() if it is being called from an interrupt context. Only API
342 functions that end in "FromISR" can be used in an interrupt. Only assert if
343 the critical nesting count is 1 to protect against recursive calls if the
344 assert function also uses a critical section. */
345 if( ulCriticalNesting == 1 )
346 {
347 configASSERT( ulPortInterruptNesting == 0 );
348 }
349 }
350 /*-----------------------------------------------------------*/
351
vPortExitCritical(void)352 void vPortExitCritical( void )
353 {
354 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
355 {
356 /* Decrement the nesting count as the critical section is being
357 exited. */
358 ulCriticalNesting--;
359
360 /* If the nesting level has reached zero then all interrupt
361 priorities must be re-enabled. */
362 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
363 {
364 /* Critical nesting has reached zero so all interrupt priorities
365 should be unmasked. */
366 portCLEAR_INTERRUPT_MASK();
367 }
368 }
369 }
370 /*-----------------------------------------------------------*/
371
FreeRTOS_Tick_Handler(void)372 void FreeRTOS_Tick_Handler( void )
373 {
374 /* Set interrupt mask before altering scheduler structures. The tick
375 handler runs at the lowest priority, so interrupts cannot already be masked,
376 so there is no need to save and restore the current mask value. */
377 __disable_irq();
378 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
379 __asm( "DSB \n"
380 "ISB \n" );
381 __enable_irq();
382
383 /* Increment the RTOS tick. */
384 if( xTaskIncrementTick() != pdFALSE )
385 {
386 ulPortYieldRequired = pdTRUE;
387 }
388
389 /* Ensure all interrupt priorities are active again. */
390 portCLEAR_INTERRUPT_MASK();
391 configCLEAR_TICK_INTERRUPT();
392 }
393 /*-----------------------------------------------------------*/
394
vPortTaskUsesFPU(void)395 void vPortTaskUsesFPU( void )
396 {
397 uint32_t ulInitialFPSCR = 0;
398
399 /* A task is registering the fact that it needs an FPU context. Set the
400 FPU flag (which is saved as part of the task context). */
401 ulPortTaskHasFPUContext = pdTRUE;
402
403 /* Initialise the floating point status register. */
404 __asm( "FMXR FPSCR, ulInitialFPSCR" );
405 }
406 /*-----------------------------------------------------------*/
407
vPortClearInterruptMask(uint32_t ulNewMaskValue)408 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
409 {
410 if( ulNewMaskValue == pdFALSE )
411 {
412 portCLEAR_INTERRUPT_MASK();
413 }
414 }
415 /*-----------------------------------------------------------*/
416
ulPortSetInterruptMask(void)417 uint32_t ulPortSetInterruptMask( void )
418 {
419 uint32_t ulReturn;
420
421 __disable_irq();
422 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
423 {
424 /* Interrupts were already masked. */
425 ulReturn = pdTRUE;
426 }
427 else
428 {
429 ulReturn = pdFALSE;
430 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
431 __asm( "DSB \n"
432 "ISB \n" );
433 }
434 __enable_irq();
435
436 return ulReturn;
437 }
438 /*-----------------------------------------------------------*/
439
440 #if( configASSERT_DEFINED == 1 )
441
vPortValidateInterruptPriority(void)442 void vPortValidateInterruptPriority( void )
443 {
444 /* The following assertion will fail if a service routine (ISR) for
445 an interrupt that has been assigned a priority above
446 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
447 function. ISR safe FreeRTOS API functions must *only* be called
448 from interrupts that have been assigned a priority at or below
449 configMAX_SYSCALL_INTERRUPT_PRIORITY.
450
451 Numerically low interrupt priority numbers represent logically high
452 interrupt priorities, therefore the priority of the interrupt must
453 be set to a value equal to or numerically *higher* than
454 configMAX_SYSCALL_INTERRUPT_PRIORITY.
455
456 FreeRTOS maintains separate thread and ISR API functions to ensure
457 interrupt entry is as fast and simple as possible.
458
459 The following links provide detailed information:
460 https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
461 https://www.FreeRTOS.org/FAQHelp.html */
462 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
463
464 /* Priority grouping: The interrupt controller (GIC) allows the bits
465 that define each interrupt's priority to be split between bits that
466 define the interrupt's pre-emption priority bits and bits that define
467 the interrupt's sub-priority. For simplicity all bits must be defined
468 to be pre-emption priority bits. The following assertion will fail if
469 this is not the case (if some bits represent a sub-priority).
470
471 The priority grouping is configured by the GIC's binary point register
472 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
473 possible value (which may be above 0). */
474 configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
475 }
476
477 #endif /* configASSERT_DEFINED */
478
