1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*
30 Changes between V1.2.4 and V1.2.5
31
32 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
33 interrupt flag setting. Using the two bits defined within
34 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
35 before the test was performed.
36
37 Changes from V1.2.5
38
39 + Set the interrupt vector address to 0x08. Previously it was at the
40 incorrect address for compatibility mode of 0x18.
41
42 Changes from V2.1.1
43
44 + PCLATU and PCLATH are now saved as part of the context. This allows
45 function pointers to be used within tasks. Thanks to Javier Espeche
46 for the enhancement.
47
48 Changes from V2.3.1
49
50 + TABLAT is now saved as part of the task context.
51
52 Changes from V3.2.0
53
54 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
55 value and does not write to the register.
56 */
57
58 /* Scheduler include files. */
59 #include "FreeRTOS.h"
60 #include "task.h"
61
62 /* MPLAB library include file. */
63 #include "timers.h"
64
65 /*-----------------------------------------------------------
66 * Implementation of functions defined in portable.h for the PIC port.
67 *----------------------------------------------------------*/
68
69 /* Hardware setup for tick. */
70 #define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
71
72 /* Initial interrupt enable state for newly created tasks. This value is
73 copied into INTCON when a task switches in for the first time. */
74 #define portINITAL_INTERRUPT_STATE 0xc0
75
76 /* Just the bit within INTCON for the global interrupt flag. */
77 #define portGLOBAL_INTERRUPT_FLAG 0x80
78
79 /* Constant used for context switch macro when we require the interrupt
80 enable state to be unchanged when the interrupted task is switched back in. */
81 #define portINTERRUPTS_UNCHANGED 0x00
82
83 /* Some memory areas get saved as part of the task context. These memory
84 area's get used by the compiler for temporary storage, especially when
85 performing mathematical operations, or when using 32bit data types. This
86 constant defines the size of memory area which must be saved. */
87 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
88
89 /* We require the address of the pxCurrentTCB variable, but don't want to know
90 any details of its type. */
91 typedef void TCB_t;
92 extern volatile TCB_t * volatile pxCurrentTCB;
93
94 /* IO port constants. */
95 #define portBIT_SET ( ( uint8_t ) 1 )
96 #define portBIT_CLEAR ( ( uint8_t ) 0 )
97
98 /*
99 * The serial port ISR's are defined in serial.c, but are called from portable
100 * as they use the same vector as the tick ISR.
101 */
102 void vSerialTxISR( void );
103 void vSerialRxISR( void );
104
105 /*
106 * Perform hardware setup to enable ticks.
107 */
108 static void prvSetupTimerInterrupt( void );
109
110 /*
111 * ISR to maintain the tick, and perform tick context switches if the
112 * preemptive scheduler is being used.
113 */
114 static void prvTickISR( void );
115
116 /*
117 * ISR placed on the low priority vector. This calls the appropriate ISR for
118 * the actual interrupt.
119 */
120 static void prvLowInterrupt( void );
121
122 /*
123 * Macro that pushes all the registers that make up the context of a task onto
124 * the stack, then saves the new top of stack into the TCB.
125 *
126 * If this is called from an ISR then the interrupt enable bits must have been
127 * set for the ISR to ever get called. Therefore we want to save the INTCON
128 * register with the enable bits forced to be set - and ucForcedInterruptFlags
129 * must contain these bit settings. This means the interrupts will again be
130 * enabled when the interrupted task is switched back in.
131 *
132 * If this is called from a manual context switch (i.e. from a call to yield),
133 * then we want to save the INTCON so it is restored with its current state,
134 * and ucForcedInterruptFlags must be 0. This allows a yield from within
135 * a critical section.
136 *
137 * The compiler uses some locations at the bottom of the memory for temporary
138 * storage during math and other computations. This is especially true if
139 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
140 * and MATH_DATA sections have to be stored in there entirety as part of a task
141 * context. This macro stores from data address 0x00 to
142 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
143 * applications but you should check the map file for your project to ensure
144 * this is sufficient for your needs. It is not clear whether this size is
145 * fixed for all compilations or has the potential to be program specific.
146 */
147 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
148 { \
149 _asm \
150 /* Save the status and WREG registers first, as these will get modified \
151 by the operations below. */ \
152 MOVFF WREG, PREINC1 \
153 MOVFF STATUS, PREINC1 \
154 /* Save the INTCON register with the appropriate bits forced if \
155 necessary - as described above. */ \
156 MOVFF INTCON, WREG \
157 IORLW ucForcedInterruptFlags \
158 MOVFF WREG, PREINC1 \
159 _endasm \
160 \
161 portDISABLE_INTERRUPTS(); \
162 \
163 _asm \
164 /* Store the necessary registers to the stack. */ \
165 MOVFF BSR, PREINC1 \
166 MOVFF FSR2L, PREINC1 \
167 MOVFF FSR2H, PREINC1 \
168 MOVFF FSR0L, PREINC1 \
169 MOVFF FSR0H, PREINC1 \
170 MOVFF TABLAT, PREINC1 \
171 MOVFF TBLPTRU, PREINC1 \
172 MOVFF TBLPTRH, PREINC1 \
173 MOVFF TBLPTRL, PREINC1 \
174 MOVFF PRODH, PREINC1 \
175 MOVFF PRODL, PREINC1 \
176 MOVFF PCLATU, PREINC1 \
177 MOVFF PCLATH, PREINC1 \
178 /* Store the .tempdata and MATH_DATA areas as described above. */ \
179 CLRF FSR0L, 0 \
180 CLRF FSR0H, 0 \
181 MOVFF POSTINC0, PREINC1 \
182 MOVFF POSTINC0, PREINC1 \
183 MOVFF POSTINC0, PREINC1 \
184 MOVFF POSTINC0, PREINC1 \
185 MOVFF POSTINC0, PREINC1 \
186 MOVFF POSTINC0, PREINC1 \
187 MOVFF POSTINC0, PREINC1 \
188 MOVFF POSTINC0, PREINC1 \
189 MOVFF POSTINC0, PREINC1 \
190 MOVFF POSTINC0, PREINC1 \
191 MOVFF POSTINC0, PREINC1 \
192 MOVFF POSTINC0, PREINC1 \
193 MOVFF POSTINC0, PREINC1 \
194 MOVFF POSTINC0, PREINC1 \
195 MOVFF POSTINC0, PREINC1 \
196 MOVFF POSTINC0, PREINC1 \
197 MOVFF POSTINC0, PREINC1 \
198 MOVFF POSTINC0, PREINC1 \
199 MOVFF POSTINC0, PREINC1 \
200 MOVFF INDF0, PREINC1 \
201 MOVFF FSR0L, PREINC1 \
202 MOVFF FSR0H, PREINC1 \
203 /* Store the hardware stack pointer in a temp register before we \
204 modify it. */ \
205 MOVFF STKPTR, FSR0L \
206 _endasm \
207 \
208 /* Store each address from the hardware stack. */ \
209 while( STKPTR > ( uint8_t ) 0 ) \
210 { \
211 _asm \
212 MOVFF TOSL, PREINC1 \
213 MOVFF TOSH, PREINC1 \
214 MOVFF TOSU, PREINC1 \
215 POP \
216 _endasm \
217 } \
218 \
219 _asm \
220 /* Store the number of addresses on the hardware stack (from the \
221 temporary register). */ \
222 MOVFF FSR0L, PREINC1 \
223 MOVF PREINC1, 1, 0 \
224 _endasm \
225 \
226 /* Save the new top of the software stack in the TCB. */ \
227 _asm \
228 MOVFF pxCurrentTCB, FSR0L \
229 MOVFF pxCurrentTCB + 1, FSR0H \
230 MOVFF FSR1L, POSTINC0 \
231 MOVFF FSR1H, POSTINC0 \
232 _endasm \
233 }
234 /*-----------------------------------------------------------*/
235
236 /*
237 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
238 * details.
239 */
240 #define portRESTORE_CONTEXT() \
241 { \
242 _asm \
243 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
244 MOVFF pxCurrentTCB, FSR0L \
245 MOVFF pxCurrentTCB + 1, FSR0H \
246 \
247 /* De-reference FSR0 to set the address it holds into FSR1. \
248 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
249 MOVFF POSTINC0, FSR1L \
250 MOVFF POSTINC0, FSR1H \
251 \
252 /* How many return addresses are there on the hardware stack? Discard \
253 the first byte as we are pointing to the next free space. */ \
254 MOVFF POSTDEC1, FSR0L \
255 MOVFF POSTDEC1, FSR0L \
256 _endasm \
257 \
258 /* Fill the hardware stack from our software stack. */ \
259 STKPTR = 0; \
260 \
261 while( STKPTR < FSR0L ) \
262 { \
263 _asm \
264 PUSH \
265 MOVF POSTDEC1, 0, 0 \
266 MOVWF TOSU, 0 \
267 MOVF POSTDEC1, 0, 0 \
268 MOVWF TOSH, 0 \
269 MOVF POSTDEC1, 0, 0 \
270 MOVWF TOSL, 0 \
271 _endasm \
272 } \
273 \
274 _asm \
275 /* Restore the .tmpdata and MATH_DATA memory. */ \
276 MOVFF POSTDEC1, FSR0H \
277 MOVFF POSTDEC1, FSR0L \
278 MOVFF POSTDEC1, POSTDEC0 \
279 MOVFF POSTDEC1, POSTDEC0 \
280 MOVFF POSTDEC1, POSTDEC0 \
281 MOVFF POSTDEC1, POSTDEC0 \
282 MOVFF POSTDEC1, POSTDEC0 \
283 MOVFF POSTDEC1, POSTDEC0 \
284 MOVFF POSTDEC1, POSTDEC0 \
285 MOVFF POSTDEC1, POSTDEC0 \
286 MOVFF POSTDEC1, POSTDEC0 \
287 MOVFF POSTDEC1, POSTDEC0 \
288 MOVFF POSTDEC1, POSTDEC0 \
289 MOVFF POSTDEC1, POSTDEC0 \
290 MOVFF POSTDEC1, POSTDEC0 \
291 MOVFF POSTDEC1, POSTDEC0 \
292 MOVFF POSTDEC1, POSTDEC0 \
293 MOVFF POSTDEC1, POSTDEC0 \
294 MOVFF POSTDEC1, POSTDEC0 \
295 MOVFF POSTDEC1, POSTDEC0 \
296 MOVFF POSTDEC1, POSTDEC0 \
297 MOVFF POSTDEC1, INDF0 \
298 /* Restore the other registers forming the tasks context. */ \
299 MOVFF POSTDEC1, PCLATH \
300 MOVFF POSTDEC1, PCLATU \
301 MOVFF POSTDEC1, PRODL \
302 MOVFF POSTDEC1, PRODH \
303 MOVFF POSTDEC1, TBLPTRL \
304 MOVFF POSTDEC1, TBLPTRH \
305 MOVFF POSTDEC1, TBLPTRU \
306 MOVFF POSTDEC1, TABLAT \
307 MOVFF POSTDEC1, FSR0H \
308 MOVFF POSTDEC1, FSR0L \
309 MOVFF POSTDEC1, FSR2H \
310 MOVFF POSTDEC1, FSR2L \
311 MOVFF POSTDEC1, BSR \
312 /* The next byte is the INTCON register. Read this into WREG as some \
313 manipulation is required. */ \
314 MOVFF POSTDEC1, WREG \
315 _endasm \
316 \
317 /* From the INTCON register, only the interrupt enable bits form part \
318 of the tasks context. It is perfectly legitimate for another task to \
319 have modified any other bits. We therefore only restore the top two bits. \
320 */ \
321 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
322 { \
323 _asm \
324 MOVFF POSTDEC1, STATUS \
325 MOVFF POSTDEC1, WREG \
326 /* Return enabling interrupts. */ \
327 RETFIE 0 \
328 _endasm \
329 } \
330 else \
331 { \
332 _asm \
333 MOVFF POSTDEC1, STATUS \
334 MOVFF POSTDEC1, WREG \
335 /* Return without effecting interrupts. The context may have \
336 been saved from a critical region. */ \
337 RETURN 0 \
338 _endasm \
339 } \
340 }
341 /*-----------------------------------------------------------*/
342
343 /*
344 * See header file for description.
345 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)346 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
347 {
348 uint32_t ulAddress;
349 uint8_t ucBlock;
350
351 /* Place a few bytes of known values on the bottom of the stack.
352 This is just useful for debugging. */
353
354 *pxTopOfStack = 0x11;
355 pxTopOfStack++;
356 *pxTopOfStack = 0x22;
357 pxTopOfStack++;
358 *pxTopOfStack = 0x33;
359 pxTopOfStack++;
360
361
362 /* Simulate how the stack would look after a call to vPortYield() generated
363 by the compiler.
364
365 First store the function parameters. This is where the task will expect to
366 find them when it starts running. */
367 ulAddress = ( uint32_t ) pvParameters;
368 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
369 pxTopOfStack++;
370
371 ulAddress >>= 8;
372 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
373 pxTopOfStack++;
374
375 /* Next we just leave a space. When a context is saved the stack pointer
376 is incremented before it is used so as not to corrupt whatever the stack
377 pointer is actually pointing to. This is especially necessary during
378 function epilogue code generated by the compiler. */
379 *pxTopOfStack = 0x44;
380 pxTopOfStack++;
381
382 /* Next are all the registers that form part of the task context. */
383
384 *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
385 pxTopOfStack++;
386
387 *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
388 pxTopOfStack++;
389
390 /* INTCON is saved with interrupts enabled. */
391 *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
392 pxTopOfStack++;
393
394 *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
395 pxTopOfStack++;
396
397 *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
398 pxTopOfStack++;
399
400 *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
401 pxTopOfStack++;
402
403 *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
404 pxTopOfStack++;
405
406 *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
407 pxTopOfStack++;
408
409 *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
410 pxTopOfStack++;
411
412 *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
413 pxTopOfStack++;
414
415 *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
416 pxTopOfStack++;
417
418 *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
419 pxTopOfStack++;
420
421 *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
422 pxTopOfStack++;
423
424 *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
425 pxTopOfStack++;
426
427 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
428 pxTopOfStack++;
429
430 *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
431 pxTopOfStack++;
432
433 /* Next the .tmpdata and MATH_DATA sections. */
434 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
435 {
436 *pxTopOfStack = ( StackType_t ) ucBlock;
437 *pxTopOfStack++;
438 }
439
440 /* Store the top of the global data section. */
441 *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
442 pxTopOfStack++;
443
444 *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
445 pxTopOfStack++;
446
447 /* The only function return address so far is the address of the
448 task. */
449 ulAddress = ( uint32_t ) pxCode;
450
451 /* TOS low. */
452 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
453 pxTopOfStack++;
454 ulAddress >>= 8;
455
456 /* TOS high. */
457 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
458 pxTopOfStack++;
459 ulAddress >>= 8;
460
461 /* TOS even higher. */
462 *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
463 pxTopOfStack++;
464
465 /* Store the number of return addresses on the hardware stack - so far only
466 the address of the task entry point. */
467 *pxTopOfStack = ( StackType_t ) 1;
468 pxTopOfStack++;
469
470 return pxTopOfStack;
471 }
472 /*-----------------------------------------------------------*/
473
xPortStartScheduler(void)474 BaseType_t xPortStartScheduler( void )
475 {
476 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
477 prvSetupTimerInterrupt();
478
479 /* Restore the context of the first task to run. */
480 portRESTORE_CONTEXT();
481
482 /* Should not get here. Use the function name to stop compiler warnings. */
483 ( void ) prvLowInterrupt;
484 ( void ) prvTickISR;
485
486 return pdTRUE;
487 }
488 /*-----------------------------------------------------------*/
489
vPortEndScheduler(void)490 void vPortEndScheduler( void )
491 {
492 /* It is unlikely that the scheduler for the PIC port will get stopped
493 once running. If required disable the tick interrupt here, then return
494 to xPortStartScheduler(). */
495 }
496 /*-----------------------------------------------------------*/
497
498 /*
499 * Manual context switch. This is similar to the tick context switch,
500 * but does not increment the tick count. It must be identical to the
501 * tick context switch in how it stores the stack of a task.
502 */
vPortYield(void)503 void vPortYield( void )
504 {
505 /* This can get called with interrupts either enabled or disabled. We
506 will save the INTCON register with the interrupt enable bits unmodified. */
507 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
508
509 /* Switch to the highest priority task that is ready to run. */
510 vTaskSwitchContext();
511
512 /* Start executing the task we have just switched to. */
513 portRESTORE_CONTEXT();
514 }
515 /*-----------------------------------------------------------*/
516
517 /*
518 * Vector for ISR. Nothing here must alter any registers!
519 */
520 #pragma code high_vector=0x08
prvLowInterrupt(void)521 static void prvLowInterrupt( void )
522 {
523 /* Was the interrupt the tick? */
524 if( PIR1bits.CCP1IF )
525 {
526 _asm
527 goto prvTickISR
528 _endasm
529 }
530
531 /* Was the interrupt a byte being received? */
532 if( PIR1bits.RCIF )
533 {
534 _asm
535 goto vSerialRxISR
536 _endasm
537 }
538
539 /* Was the interrupt the Tx register becoming empty? */
540 if( PIR1bits.TXIF )
541 {
542 if( PIE1bits.TXIE )
543 {
544 _asm
545 goto vSerialTxISR
546 _endasm
547 }
548 }
549 }
550 #pragma code
551
552 /*-----------------------------------------------------------*/
553
554 /*
555 * ISR for the tick.
556 * This increments the tick count and, if using the preemptive scheduler,
557 * performs a context switch. This must be identical to the manual
558 * context switch in how it stores the context of a task.
559 */
560 static void prvTickISR( void )
561 {
562 /* Interrupts must have been enabled for the ISR to fire, so we have to
563 save the context with interrupts enabled. */
564 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
565 PIR1bits.CCP1IF = 0;
566
567 /* Maintain the tick count. */
568 if( xTaskIncrementTick() != pdFALSE )
569 {
570 /* Switch to the highest priority task that is ready to run. */
571 vTaskSwitchContext();
572 }
573
574 portRESTORE_CONTEXT();
575 }
576 /*-----------------------------------------------------------*/
577
578 /*
579 * Setup a timer for a regular tick.
580 */
581 static void prvSetupTimerInterrupt( void )
582 {
583 const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
584 uint32_t ulCompareValue;
585 uint8_t ucByte;
586
587 /* Interrupts are disabled when this function is called.
588
589 Setup CCP1 to provide the tick interrupt using a compare match on timer
590 1.
591
592 Clear the time count then setup timer. */
593 TMR1H = ( uint8_t ) 0x00;
594 TMR1L = ( uint8_t ) 0x00;
595
596 /* Set the compare match value. */
597 ulCompareValue = ulConstCompareValue;
598 CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
599 ulCompareValue >>= ( uint32_t ) 8;
600 CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
601
602 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
603 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
604 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
605 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
606 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
607
608 /* We are only going to use the global interrupt bit, so set the peripheral
609 bit to true. */
610 INTCONbits.GIEL = portBIT_SET;
611
612 /* Provided library function for setting up the timer that will produce the
613 tick. */
614 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
615 }
616
