1 //*---------------------------------------------------------------------------- 2 //* ATMEL Microcontroller Software Support - ROUSSET - 3 //*---------------------------------------------------------------------------- 4 //* The software is delivered "AS IS" without warranty or condition of any 5 //* kind, either express, implied or statutory. This includes without 6 //* limitation any warranty or condition with respect to merchantability or 7 //* fitness for any particular purpose, or against the infringements of 8 //* intellectual property rights of others. 9 //*---------------------------------------------------------------------------- 10 //* File Name : lib_AT91SAM7S64.h 11 //* Object : AT91SAM7S64 inlined functions 12 //* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) 13 //* 14 //* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// 15 //* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// 16 //* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// 17 //* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// 18 //* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// 19 //* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// 20 //* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// 21 //* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// 22 //* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// 23 //* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// 24 //* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// 25 //* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// 26 //* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// 27 //* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// 28 //*---------------------------------------------------------------------------- 29 30 #ifndef lib_AT91SAM7S64_H 31 #define lib_AT91SAM7S64_H 32 33 /* ***************************************************************************** 34 SOFTWARE API FOR MC 35 ***************************************************************************** */ 36 37 #define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key 38 39 //*---------------------------------------------------------------------------- 40 //* \fn AT91F_MC_Remap 41 //* \brief Make Remap 42 //*---------------------------------------------------------------------------- AT91F_MC_Remap(void)43__inline void AT91F_MC_Remap (void) // 44 { 45 AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; 46 47 pMC->MC_RCR = AT91C_MC_RCB; 48 } 49 50 //*---------------------------------------------------------------------------- 51 //* \fn AT91F_MC_EFC_CfgModeReg 52 //* \brief Configure the EFC Mode Register of the MC controller 53 //*---------------------------------------------------------------------------- AT91F_MC_EFC_CfgModeReg(AT91PS_MC pMC,unsigned int mode)54__inline void AT91F_MC_EFC_CfgModeReg ( 55 AT91PS_MC pMC, // pointer to a MC controller 56 unsigned int mode) // mode register 57 { 58 // Write to the FMR register 59 pMC->MC_FMR = mode; 60 } 61 62 //*---------------------------------------------------------------------------- 63 //* \fn AT91F_MC_EFC_GetModeReg 64 //* \brief Return MC EFC Mode Regsiter 65 //*---------------------------------------------------------------------------- AT91F_MC_EFC_GetModeReg(AT91PS_MC pMC)66__inline unsigned int AT91F_MC_EFC_GetModeReg( 67 AT91PS_MC pMC) // pointer to a MC controller 68 { 69 return pMC->MC_FMR; 70 } 71 72 //*---------------------------------------------------------------------------- 73 //* \fn AT91F_MC_EFC_ComputeFMCN 74 //* \brief Return MC EFC Mode Regsiter 75 //*---------------------------------------------------------------------------- AT91F_MC_EFC_ComputeFMCN(int master_clock)76__inline unsigned int AT91F_MC_EFC_ComputeFMCN( 77 int master_clock) // master clock in Hz 78 { 79 return (master_clock/1000000 +2); 80 } 81 82 //*---------------------------------------------------------------------------- 83 //* \fn AT91F_MC_EFC_PerformCmd 84 //* \brief Perform EFC Command 85 //*---------------------------------------------------------------------------- AT91F_MC_EFC_PerformCmd(AT91PS_MC pMC,unsigned int transfer_cmd)86__inline void AT91F_MC_EFC_PerformCmd ( 87 AT91PS_MC pMC, // pointer to a MC controller 88 unsigned int transfer_cmd) 89 { 90 pMC->MC_FCR = transfer_cmd; 91 } 92 93 //*---------------------------------------------------------------------------- 94 //* \fn AT91F_MC_EFC_GetStatus 95 //* \brief Return MC EFC Status 96 //*---------------------------------------------------------------------------- AT91F_MC_EFC_GetStatus(AT91PS_MC pMC)97__inline unsigned int AT91F_MC_EFC_GetStatus( 98 AT91PS_MC pMC) // pointer to a MC controller 99 { 100 return pMC->MC_FSR; 101 } 102 103 //*---------------------------------------------------------------------------- 104 //* \fn AT91F_MC_EFC_IsInterruptMasked 105 //* \brief Test if EFC MC Interrupt is Masked 106 //*---------------------------------------------------------------------------- AT91F_MC_EFC_IsInterruptMasked(AT91PS_MC pMC,unsigned int flag)107__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( 108 AT91PS_MC pMC, // \arg pointer to a MC controller 109 unsigned int flag) // \arg flag to be tested 110 { 111 return (AT91F_MC_EFC_GetModeReg(pMC) & flag); 112 } 113 114 //*---------------------------------------------------------------------------- 115 //* \fn AT91F_MC_EFC_IsInterruptSet 116 //* \brief Test if EFC MC Interrupt is Set 117 //*---------------------------------------------------------------------------- AT91F_MC_EFC_IsInterruptSet(AT91PS_MC pMC,unsigned int flag)118__inline unsigned int AT91F_MC_EFC_IsInterruptSet( 119 AT91PS_MC pMC, // \arg pointer to a MC controller 120 unsigned int flag) // \arg flag to be tested 121 { 122 return (AT91F_MC_EFC_GetStatus(pMC) & flag); 123 } 124 125 /* ***************************************************************************** 126 SOFTWARE API FOR PDC 127 ***************************************************************************** */ 128 //*---------------------------------------------------------------------------- 129 //* \fn AT91F_PDC_SetNextRx 130 //* \brief Set the next receive transfer descriptor 131 //*---------------------------------------------------------------------------- AT91F_PDC_SetNextRx(AT91PS_PDC pPDC,char * address,unsigned int bytes)132__inline void AT91F_PDC_SetNextRx ( 133 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 134 char *address, // \arg address to the next bloc to be received 135 unsigned int bytes) // \arg number of bytes to be received 136 { 137 pPDC->PDC_RNPR = (unsigned int) address; 138 pPDC->PDC_RNCR = bytes; 139 } 140 141 //*---------------------------------------------------------------------------- 142 //* \fn AT91F_PDC_SetNextTx 143 //* \brief Set the next transmit transfer descriptor 144 //*---------------------------------------------------------------------------- AT91F_PDC_SetNextTx(AT91PS_PDC pPDC,char * address,unsigned int bytes)145__inline void AT91F_PDC_SetNextTx ( 146 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 147 char *address, // \arg address to the next bloc to be transmitted 148 unsigned int bytes) // \arg number of bytes to be transmitted 149 { 150 pPDC->PDC_TNPR = (unsigned int) address; 151 pPDC->PDC_TNCR = bytes; 152 } 153 154 //*---------------------------------------------------------------------------- 155 //* \fn AT91F_PDC_SetRx 156 //* \brief Set the receive transfer descriptor 157 //*---------------------------------------------------------------------------- AT91F_PDC_SetRx(AT91PS_PDC pPDC,char * address,unsigned int bytes)158__inline void AT91F_PDC_SetRx ( 159 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 160 char *address, // \arg address to the next bloc to be received 161 unsigned int bytes) // \arg number of bytes to be received 162 { 163 pPDC->PDC_RPR = (unsigned int) address; 164 pPDC->PDC_RCR = bytes; 165 } 166 167 //*---------------------------------------------------------------------------- 168 //* \fn AT91F_PDC_SetTx 169 //* \brief Set the transmit transfer descriptor 170 //*---------------------------------------------------------------------------- AT91F_PDC_SetTx(AT91PS_PDC pPDC,char * address,unsigned int bytes)171__inline void AT91F_PDC_SetTx ( 172 AT91PS_PDC pPDC, // \arg pointer to a PDC controller 173 char *address, // \arg address to the next bloc to be transmitted 174 unsigned int bytes) // \arg number of bytes to be transmitted 175 { 176 pPDC->PDC_TPR = (unsigned int) address; 177 pPDC->PDC_TCR = bytes; 178 } 179 180 //*---------------------------------------------------------------------------- 181 //* \fn AT91F_PDC_EnableTx 182 //* \brief Enable transmit 183 //*---------------------------------------------------------------------------- AT91F_PDC_EnableTx(AT91PS_PDC pPDC)184__inline void AT91F_PDC_EnableTx ( 185 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 186 { 187 pPDC->PDC_PTCR = AT91C_PDC_TXTEN; 188 } 189 190 //*---------------------------------------------------------------------------- 191 //* \fn AT91F_PDC_EnableRx 192 //* \brief Enable receive 193 //*---------------------------------------------------------------------------- AT91F_PDC_EnableRx(AT91PS_PDC pPDC)194__inline void AT91F_PDC_EnableRx ( 195 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 196 { 197 pPDC->PDC_PTCR = AT91C_PDC_RXTEN; 198 } 199 200 //*---------------------------------------------------------------------------- 201 //* \fn AT91F_PDC_DisableTx 202 //* \brief Disable transmit 203 //*---------------------------------------------------------------------------- AT91F_PDC_DisableTx(AT91PS_PDC pPDC)204__inline void AT91F_PDC_DisableTx ( 205 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 206 { 207 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; 208 } 209 210 //*---------------------------------------------------------------------------- 211 //* \fn AT91F_PDC_DisableRx 212 //* \brief Disable receive 213 //*---------------------------------------------------------------------------- AT91F_PDC_DisableRx(AT91PS_PDC pPDC)214__inline void AT91F_PDC_DisableRx ( 215 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 216 { 217 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; 218 } 219 220 //*---------------------------------------------------------------------------- 221 //* \fn AT91F_PDC_IsTxEmpty 222 //* \brief Test if the current transfer descriptor has been sent 223 //*---------------------------------------------------------------------------- AT91F_PDC_IsTxEmpty(AT91PS_PDC pPDC)224__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete 225 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 226 { 227 return !(pPDC->PDC_TCR); 228 } 229 230 //*---------------------------------------------------------------------------- 231 //* \fn AT91F_PDC_IsNextTxEmpty 232 //* \brief Test if the next transfer descriptor has been moved to the current td 233 //*---------------------------------------------------------------------------- AT91F_PDC_IsNextTxEmpty(AT91PS_PDC pPDC)234__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete 235 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 236 { 237 return !(pPDC->PDC_TNCR); 238 } 239 240 //*---------------------------------------------------------------------------- 241 //* \fn AT91F_PDC_IsRxEmpty 242 //* \brief Test if the current transfer descriptor has been filled 243 //*---------------------------------------------------------------------------- AT91F_PDC_IsRxEmpty(AT91PS_PDC pPDC)244__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete 245 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 246 { 247 return !(pPDC->PDC_RCR); 248 } 249 250 //*---------------------------------------------------------------------------- 251 //* \fn AT91F_PDC_IsNextRxEmpty 252 //* \brief Test if the next transfer descriptor has been moved to the current td 253 //*---------------------------------------------------------------------------- AT91F_PDC_IsNextRxEmpty(AT91PS_PDC pPDC)254__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete 255 AT91PS_PDC pPDC ) // \arg pointer to a PDC controller 256 { 257 return !(pPDC->PDC_RNCR); 258 } 259 260 //*---------------------------------------------------------------------------- 261 //* \fn AT91F_PDC_Open 262 //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX 263 //*---------------------------------------------------------------------------- AT91F_PDC_Open(AT91PS_PDC pPDC)264__inline void AT91F_PDC_Open ( 265 AT91PS_PDC pPDC) // \arg pointer to a PDC controller 266 { 267 //* Disable the RX and TX PDC transfer requests 268 AT91F_PDC_DisableRx(pPDC); 269 AT91F_PDC_DisableTx(pPDC); 270 271 //* Reset all Counter register Next buffer first 272 AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); 273 AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); 274 AT91F_PDC_SetTx(pPDC, (char *) 0, 0); 275 AT91F_PDC_SetRx(pPDC, (char *) 0, 0); 276 277 //* Enable the RX and TX PDC transfer requests 278 AT91F_PDC_EnableRx(pPDC); 279 AT91F_PDC_EnableTx(pPDC); 280 } 281 282 //*---------------------------------------------------------------------------- 283 //* \fn AT91F_PDC_Close 284 //* \brief Close PDC: disable TX and RX reset transfer descriptors 285 //*---------------------------------------------------------------------------- AT91F_PDC_Close(AT91PS_PDC pPDC)286__inline void AT91F_PDC_Close ( 287 AT91PS_PDC pPDC) // \arg pointer to a PDC controller 288 { 289 //* Disable the RX and TX PDC transfer requests 290 AT91F_PDC_DisableRx(pPDC); 291 AT91F_PDC_DisableTx(pPDC); 292 293 //* Reset all Counter register Next buffer first 294 AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); 295 AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); 296 AT91F_PDC_SetTx(pPDC, (char *) 0, 0); 297 AT91F_PDC_SetRx(pPDC, (char *) 0, 0); 298 299 } 300 301 //*---------------------------------------------------------------------------- 302 //* \fn AT91F_PDC_SendFrame 303 //* \brief Close PDC: disable TX and RX reset transfer descriptors 304 //*---------------------------------------------------------------------------- AT91F_PDC_SendFrame(AT91PS_PDC pPDC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)305__inline unsigned int AT91F_PDC_SendFrame( 306 AT91PS_PDC pPDC, 307 char *pBuffer, 308 unsigned int szBuffer, 309 char *pNextBuffer, 310 unsigned int szNextBuffer ) 311 { 312 if (AT91F_PDC_IsTxEmpty(pPDC)) { 313 //* Buffer and next buffer can be initialized 314 AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); 315 AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); 316 return 2; 317 } 318 else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { 319 //* Only one buffer can be initialized 320 AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); 321 return 1; 322 } 323 else { 324 //* All buffer are in use... 325 return 0; 326 } 327 } 328 329 //*---------------------------------------------------------------------------- 330 //* \fn AT91F_PDC_ReceiveFrame 331 //* \brief Close PDC: disable TX and RX reset transfer descriptors 332 //*---------------------------------------------------------------------------- AT91F_PDC_ReceiveFrame(AT91PS_PDC pPDC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)333__inline unsigned int AT91F_PDC_ReceiveFrame ( 334 AT91PS_PDC pPDC, 335 char *pBuffer, 336 unsigned int szBuffer, 337 char *pNextBuffer, 338 unsigned int szNextBuffer ) 339 { 340 if (AT91F_PDC_IsRxEmpty(pPDC)) { 341 //* Buffer and next buffer can be initialized 342 AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); 343 AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); 344 return 2; 345 } 346 else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { 347 //* Only one buffer can be initialized 348 AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); 349 return 1; 350 } 351 else { 352 //* All buffer are in use... 353 return 0; 354 } 355 } 356 /* ***************************************************************************** 357 SOFTWARE API FOR DBGU 358 ***************************************************************************** */ 359 //*---------------------------------------------------------------------------- 360 //* \fn AT91F_DBGU_InterruptEnable 361 //* \brief Enable DBGU Interrupt 362 //*---------------------------------------------------------------------------- AT91F_DBGU_InterruptEnable(AT91PS_DBGU pDbgu,unsigned int flag)363__inline void AT91F_DBGU_InterruptEnable( 364 AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller 365 unsigned int flag) // \arg dbgu interrupt to be enabled 366 { 367 pDbgu->DBGU_IER = flag; 368 } 369 370 //*---------------------------------------------------------------------------- 371 //* \fn AT91F_DBGU_InterruptDisable 372 //* \brief Disable DBGU Interrupt 373 //*---------------------------------------------------------------------------- AT91F_DBGU_InterruptDisable(AT91PS_DBGU pDbgu,unsigned int flag)374__inline void AT91F_DBGU_InterruptDisable( 375 AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller 376 unsigned int flag) // \arg dbgu interrupt to be disabled 377 { 378 pDbgu->DBGU_IDR = flag; 379 } 380 381 //*---------------------------------------------------------------------------- 382 //* \fn AT91F_DBGU_GetInterruptMaskStatus 383 //* \brief Return DBGU Interrupt Mask Status 384 //*---------------------------------------------------------------------------- AT91F_DBGU_GetInterruptMaskStatus(AT91PS_DBGU pDbgu)385__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status 386 AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller 387 { 388 return pDbgu->DBGU_IMR; 389 } 390 391 //*---------------------------------------------------------------------------- 392 //* \fn AT91F_DBGU_IsInterruptMasked 393 //* \brief Test if DBGU Interrupt is Masked 394 //*---------------------------------------------------------------------------- AT91F_DBGU_IsInterruptMasked(AT91PS_DBGU pDbgu,unsigned int flag)395__inline int AT91F_DBGU_IsInterruptMasked( 396 AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller 397 unsigned int flag) // \arg flag to be tested 398 { 399 return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); 400 } 401 402 /* ***************************************************************************** 403 SOFTWARE API FOR SSC 404 ***************************************************************************** */ 405 //* Define the standard I2S mode configuration 406 407 //* Configuration to set in the SSC Transmit Clock Mode Register 408 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits 409 //* nb_slot_by_frame : number of channels 410 #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ 411 AT91C_SSC_CKS_DIV +\ 412 AT91C_SSC_CKO_CONTINOUS +\ 413 AT91C_SSC_CKG_NONE +\ 414 AT91C_SSC_START_FALL_RF +\ 415 AT91C_SSC_STTOUT +\ 416 ((1<<16) & AT91C_SSC_STTDLY) +\ 417 ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) 418 419 420 //* Configuration to set in the SSC Transmit Frame Mode Register 421 //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits 422 //* nb_slot_by_frame : number of channels 423 #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ 424 (nb_bit_by_slot-1) +\ 425 AT91C_SSC_MSBF +\ 426 (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ 427 (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ 428 AT91C_SSC_FSOS_NEGATIVE) 429 430 431 //*---------------------------------------------------------------------------- 432 //* \fn AT91F_SSC_SetBaudrate 433 //* \brief Set the baudrate according to the CPU clock 434 //*---------------------------------------------------------------------------- AT91F_SSC_SetBaudrate(AT91PS_SSC pSSC,unsigned int mainClock,unsigned int speed)435__inline void AT91F_SSC_SetBaudrate ( 436 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 437 unsigned int mainClock, // \arg peripheral clock 438 unsigned int speed) // \arg SSC baudrate 439 { 440 unsigned int baud_value; 441 //* Define the baud rate divisor register 442 if (speed == 0) 443 baud_value = 0; 444 else 445 { 446 baud_value = (unsigned int) (mainClock * 10)/(2*speed); 447 if ((baud_value % 10) >= 5) 448 baud_value = (baud_value / 10) + 1; 449 else 450 baud_value /= 10; 451 } 452 453 pSSC->SSC_CMR = baud_value; 454 } 455 456 //*---------------------------------------------------------------------------- 457 //* \fn AT91F_SSC_Configure 458 //* \brief Configure SSC 459 //*---------------------------------------------------------------------------- AT91F_SSC_Configure(AT91PS_SSC pSSC,unsigned int syst_clock,unsigned int baud_rate,unsigned int clock_rx,unsigned int mode_rx,unsigned int clock_tx,unsigned int mode_tx)460__inline void AT91F_SSC_Configure ( 461 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 462 unsigned int syst_clock, // \arg System Clock Frequency 463 unsigned int baud_rate, // \arg Expected Baud Rate Frequency 464 unsigned int clock_rx, // \arg Receiver Clock Parameters 465 unsigned int mode_rx, // \arg mode Register to be programmed 466 unsigned int clock_tx, // \arg Transmitter Clock Parameters 467 unsigned int mode_tx) // \arg mode Register to be programmed 468 { 469 //* Disable interrupts 470 pSSC->SSC_IDR = (unsigned int) -1; 471 472 //* Reset receiver and transmitter 473 pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; 474 475 //* Define the Clock Mode Register 476 AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); 477 478 //* Write the Receive Clock Mode Register 479 pSSC->SSC_RCMR = clock_rx; 480 481 //* Write the Transmit Clock Mode Register 482 pSSC->SSC_TCMR = clock_tx; 483 484 //* Write the Receive Frame Mode Register 485 pSSC->SSC_RFMR = mode_rx; 486 487 //* Write the Transmit Frame Mode Register 488 pSSC->SSC_TFMR = mode_tx; 489 490 //* Clear Transmit and Receive Counters 491 AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); 492 493 494 } 495 496 //*---------------------------------------------------------------------------- 497 //* \fn AT91F_SSC_EnableRx 498 //* \brief Enable receiving datas 499 //*---------------------------------------------------------------------------- AT91F_SSC_EnableRx(AT91PS_SSC pSSC)500__inline void AT91F_SSC_EnableRx ( 501 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 502 { 503 //* Enable receiver 504 pSSC->SSC_CR = AT91C_SSC_RXEN; 505 } 506 507 //*---------------------------------------------------------------------------- 508 //* \fn AT91F_SSC_DisableRx 509 //* \brief Disable receiving datas 510 //*---------------------------------------------------------------------------- AT91F_SSC_DisableRx(AT91PS_SSC pSSC)511__inline void AT91F_SSC_DisableRx ( 512 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 513 { 514 //* Disable receiver 515 pSSC->SSC_CR = AT91C_SSC_RXDIS; 516 } 517 518 //*---------------------------------------------------------------------------- 519 //* \fn AT91F_SSC_EnableTx 520 //* \brief Enable sending datas 521 //*---------------------------------------------------------------------------- AT91F_SSC_EnableTx(AT91PS_SSC pSSC)522__inline void AT91F_SSC_EnableTx ( 523 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 524 { 525 //* Enable transmitter 526 pSSC->SSC_CR = AT91C_SSC_TXEN; 527 } 528 529 //*---------------------------------------------------------------------------- 530 //* \fn AT91F_SSC_DisableTx 531 //* \brief Disable sending datas 532 //*---------------------------------------------------------------------------- AT91F_SSC_DisableTx(AT91PS_SSC pSSC)533__inline void AT91F_SSC_DisableTx ( 534 AT91PS_SSC pSSC) // \arg pointer to a SSC controller 535 { 536 //* Disable transmitter 537 pSSC->SSC_CR = AT91C_SSC_TXDIS; 538 } 539 540 //*---------------------------------------------------------------------------- 541 //* \fn AT91F_SSC_EnableIt 542 //* \brief Enable SSC IT 543 //*---------------------------------------------------------------------------- AT91F_SSC_EnableIt(AT91PS_SSC pSSC,unsigned int flag)544__inline void AT91F_SSC_EnableIt ( 545 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 546 unsigned int flag) // \arg IT to be enabled 547 { 548 //* Write to the IER register 549 pSSC->SSC_IER = flag; 550 } 551 552 //*---------------------------------------------------------------------------- 553 //* \fn AT91F_SSC_DisableIt 554 //* \brief Disable SSC IT 555 //*---------------------------------------------------------------------------- AT91F_SSC_DisableIt(AT91PS_SSC pSSC,unsigned int flag)556__inline void AT91F_SSC_DisableIt ( 557 AT91PS_SSC pSSC, // \arg pointer to a SSC controller 558 unsigned int flag) // \arg IT to be disabled 559 { 560 //* Write to the IDR register 561 pSSC->SSC_IDR = flag; 562 } 563 564 //*---------------------------------------------------------------------------- 565 //* \fn AT91F_SSC_ReceiveFrame 566 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy 567 //*---------------------------------------------------------------------------- AT91F_SSC_ReceiveFrame(AT91PS_SSC pSSC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)568__inline unsigned int AT91F_SSC_ReceiveFrame ( 569 AT91PS_SSC pSSC, 570 char *pBuffer, 571 unsigned int szBuffer, 572 char *pNextBuffer, 573 unsigned int szNextBuffer ) 574 { 575 return AT91F_PDC_ReceiveFrame( 576 (AT91PS_PDC) &(pSSC->SSC_RPR), 577 pBuffer, 578 szBuffer, 579 pNextBuffer, 580 szNextBuffer); 581 } 582 583 //*---------------------------------------------------------------------------- 584 //* \fn AT91F_SSC_SendFrame 585 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy 586 //*---------------------------------------------------------------------------- AT91F_SSC_SendFrame(AT91PS_SSC pSSC,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)587__inline unsigned int AT91F_SSC_SendFrame( 588 AT91PS_SSC pSSC, 589 char *pBuffer, 590 unsigned int szBuffer, 591 char *pNextBuffer, 592 unsigned int szNextBuffer ) 593 { 594 return AT91F_PDC_SendFrame( 595 (AT91PS_PDC) &(pSSC->SSC_RPR), 596 pBuffer, 597 szBuffer, 598 pNextBuffer, 599 szNextBuffer); 600 } 601 602 //*---------------------------------------------------------------------------- 603 //* \fn AT91F_SSC_GetInterruptMaskStatus 604 //* \brief Return SSC Interrupt Mask Status 605 //*---------------------------------------------------------------------------- AT91F_SSC_GetInterruptMaskStatus(AT91PS_SSC pSsc)606__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status 607 AT91PS_SSC pSsc) // \arg pointer to a SSC controller 608 { 609 return pSsc->SSC_IMR; 610 } 611 612 //*---------------------------------------------------------------------------- 613 //* \fn AT91F_SSC_IsInterruptMasked 614 //* \brief Test if SSC Interrupt is Masked 615 //*---------------------------------------------------------------------------- AT91F_SSC_IsInterruptMasked(AT91PS_SSC pSsc,unsigned int flag)616__inline int AT91F_SSC_IsInterruptMasked( 617 AT91PS_SSC pSsc, // \arg pointer to a SSC controller 618 unsigned int flag) // \arg flag to be tested 619 { 620 return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); 621 } 622 623 /* ***************************************************************************** 624 SOFTWARE API FOR SPI 625 ***************************************************************************** */ 626 //*---------------------------------------------------------------------------- 627 //* \fn AT91F_SPI_Open 628 //* \brief Open a SPI Port 629 //*---------------------------------------------------------------------------- AT91F_SPI_Open(const unsigned int null)630__inline unsigned int AT91F_SPI_Open ( 631 const unsigned int null) // \arg 632 { 633 /* NOT DEFINED AT THIS MOMENT */ 634 return ( 0 ); 635 } 636 637 //*---------------------------------------------------------------------------- 638 //* \fn AT91F_SPI_CfgCs 639 //* \brief Configure SPI chip select register 640 //*---------------------------------------------------------------------------- AT91F_SPI_CfgCs(AT91PS_SPI pSPI,int cs,int val)641__inline void AT91F_SPI_CfgCs ( 642 AT91PS_SPI pSPI, // pointer to a SPI controller 643 int cs, // SPI cs number (0 to 3) 644 int val) // chip select register 645 { 646 //* Write to the CSR register 647 *(pSPI->SPI_CSR + cs) = val; 648 } 649 650 //*---------------------------------------------------------------------------- 651 //* \fn AT91F_SPI_EnableIt 652 //* \brief Enable SPI interrupt 653 //*---------------------------------------------------------------------------- AT91F_SPI_EnableIt(AT91PS_SPI pSPI,unsigned int flag)654__inline void AT91F_SPI_EnableIt ( 655 AT91PS_SPI pSPI, // pointer to a SPI controller 656 unsigned int flag) // IT to be enabled 657 { 658 //* Write to the IER register 659 pSPI->SPI_IER = flag; 660 } 661 662 //*---------------------------------------------------------------------------- 663 //* \fn AT91F_SPI_DisableIt 664 //* \brief Disable SPI interrupt 665 //*---------------------------------------------------------------------------- AT91F_SPI_DisableIt(AT91PS_SPI pSPI,unsigned int flag)666__inline void AT91F_SPI_DisableIt ( 667 AT91PS_SPI pSPI, // pointer to a SPI controller 668 unsigned int flag) // IT to be disabled 669 { 670 //* Write to the IDR register 671 pSPI->SPI_IDR = flag; 672 } 673 674 //*---------------------------------------------------------------------------- 675 //* \fn AT91F_SPI_Reset 676 //* \brief Reset the SPI controller 677 //*---------------------------------------------------------------------------- AT91F_SPI_Reset(AT91PS_SPI pSPI)678__inline void AT91F_SPI_Reset ( 679 AT91PS_SPI pSPI // pointer to a SPI controller 680 ) 681 { 682 //* Write to the CR register 683 pSPI->SPI_CR = AT91C_SPI_SWRST; 684 } 685 686 //*---------------------------------------------------------------------------- 687 //* \fn AT91F_SPI_Enable 688 //* \brief Enable the SPI controller 689 //*---------------------------------------------------------------------------- AT91F_SPI_Enable(AT91PS_SPI pSPI)690__inline void AT91F_SPI_Enable ( 691 AT91PS_SPI pSPI // pointer to a SPI controller 692 ) 693 { 694 //* Write to the CR register 695 pSPI->SPI_CR = AT91C_SPI_SPIEN; 696 } 697 698 //*---------------------------------------------------------------------------- 699 //* \fn AT91F_SPI_Disable 700 //* \brief Disable the SPI controller 701 //*---------------------------------------------------------------------------- AT91F_SPI_Disable(AT91PS_SPI pSPI)702__inline void AT91F_SPI_Disable ( 703 AT91PS_SPI pSPI // pointer to a SPI controller 704 ) 705 { 706 //* Write to the CR register 707 pSPI->SPI_CR = AT91C_SPI_SPIDIS; 708 } 709 710 //*---------------------------------------------------------------------------- 711 //* \fn AT91F_SPI_CfgMode 712 //* \brief Enable the SPI controller 713 //*---------------------------------------------------------------------------- AT91F_SPI_CfgMode(AT91PS_SPI pSPI,int mode)714__inline void AT91F_SPI_CfgMode ( 715 AT91PS_SPI pSPI, // pointer to a SPI controller 716 int mode) // mode register 717 { 718 //* Write to the MR register 719 pSPI->SPI_MR = mode; 720 } 721 722 //*---------------------------------------------------------------------------- 723 //* \fn AT91F_SPI_CfgPCS 724 //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected 725 //*---------------------------------------------------------------------------- AT91F_SPI_CfgPCS(AT91PS_SPI pSPI,char PCS_Device)726__inline void AT91F_SPI_CfgPCS ( 727 AT91PS_SPI pSPI, // pointer to a SPI controller 728 char PCS_Device) // PCS of the Device 729 { 730 //* Write to the MR register 731 pSPI->SPI_MR &= 0xFFF0FFFF; 732 pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); 733 } 734 735 //*---------------------------------------------------------------------------- 736 //* \fn AT91F_SPI_ReceiveFrame 737 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy 738 //*---------------------------------------------------------------------------- AT91F_SPI_ReceiveFrame(AT91PS_SPI pSPI,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)739__inline unsigned int AT91F_SPI_ReceiveFrame ( 740 AT91PS_SPI pSPI, 741 char *pBuffer, 742 unsigned int szBuffer, 743 char *pNextBuffer, 744 unsigned int szNextBuffer ) 745 { 746 return AT91F_PDC_ReceiveFrame( 747 (AT91PS_PDC) &(pSPI->SPI_RPR), 748 pBuffer, 749 szBuffer, 750 pNextBuffer, 751 szNextBuffer); 752 } 753 754 //*---------------------------------------------------------------------------- 755 //* \fn AT91F_SPI_SendFrame 756 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy 757 //*---------------------------------------------------------------------------- AT91F_SPI_SendFrame(AT91PS_SPI pSPI,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)758__inline unsigned int AT91F_SPI_SendFrame( 759 AT91PS_SPI pSPI, 760 char *pBuffer, 761 unsigned int szBuffer, 762 char *pNextBuffer, 763 unsigned int szNextBuffer ) 764 { 765 return AT91F_PDC_SendFrame( 766 (AT91PS_PDC) &(pSPI->SPI_RPR), 767 pBuffer, 768 szBuffer, 769 pNextBuffer, 770 szNextBuffer); 771 } 772 773 //*---------------------------------------------------------------------------- 774 //* \fn AT91F_SPI_Close 775 //* \brief Close SPI: disable IT disable transfert, close PDC 776 //*---------------------------------------------------------------------------- AT91F_SPI_Close(AT91PS_SPI pSPI)777__inline void AT91F_SPI_Close ( 778 AT91PS_SPI pSPI) // \arg pointer to a SPI controller 779 { 780 //* Reset all the Chip Select register 781 pSPI->SPI_CSR[0] = 0 ; 782 pSPI->SPI_CSR[1] = 0 ; 783 pSPI->SPI_CSR[2] = 0 ; 784 pSPI->SPI_CSR[3] = 0 ; 785 786 //* Reset the SPI mode 787 pSPI->SPI_MR = 0 ; 788 789 //* Disable all interrupts 790 pSPI->SPI_IDR = 0xFFFFFFFF ; 791 792 //* Abort the Peripheral Data Transfers 793 AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); 794 795 //* Disable receiver and transmitter and stop any activity immediately 796 pSPI->SPI_CR = AT91C_SPI_SPIDIS; 797 } 798 799 //*---------------------------------------------------------------------------- 800 //* \fn AT91F_SPI_PutChar 801 //* \brief Send a character,does not check if ready to send 802 //*---------------------------------------------------------------------------- AT91F_SPI_PutChar(AT91PS_SPI pSPI,unsigned int character,unsigned int cs_number)803__inline void AT91F_SPI_PutChar ( 804 AT91PS_SPI pSPI, 805 unsigned int character, 806 unsigned int cs_number ) 807 { 808 unsigned int value_for_cs; 809 value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number 810 pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); 811 } 812 813 //*---------------------------------------------------------------------------- 814 //* \fn AT91F_SPI_GetChar 815 //* \brief Receive a character,does not check if a character is available 816 //*---------------------------------------------------------------------------- AT91F_SPI_GetChar(const AT91PS_SPI pSPI)817__inline int AT91F_SPI_GetChar ( 818 const AT91PS_SPI pSPI) 819 { 820 return((pSPI->SPI_RDR) & 0xFFFF); 821 } 822 823 //*---------------------------------------------------------------------------- 824 //* \fn AT91F_SPI_GetInterruptMaskStatus 825 //* \brief Return SPI Interrupt Mask Status 826 //*---------------------------------------------------------------------------- AT91F_SPI_GetInterruptMaskStatus(AT91PS_SPI pSpi)827__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status 828 AT91PS_SPI pSpi) // \arg pointer to a SPI controller 829 { 830 return pSpi->SPI_IMR; 831 } 832 833 //*---------------------------------------------------------------------------- 834 //* \fn AT91F_SPI_IsInterruptMasked 835 //* \brief Test if SPI Interrupt is Masked 836 //*---------------------------------------------------------------------------- AT91F_SPI_IsInterruptMasked(AT91PS_SPI pSpi,unsigned int flag)837__inline int AT91F_SPI_IsInterruptMasked( 838 AT91PS_SPI pSpi, // \arg pointer to a SPI controller 839 unsigned int flag) // \arg flag to be tested 840 { 841 return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); 842 } 843 844 /* ***************************************************************************** 845 SOFTWARE API FOR PWMC 846 ***************************************************************************** */ 847 //*---------------------------------------------------------------------------- 848 //* \fn AT91F_PWM_GetStatus 849 //* \brief Return PWM Interrupt Status 850 //*---------------------------------------------------------------------------- AT91F_PWMC_GetStatus(AT91PS_PWMC pPWM)851__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status 852 AT91PS_PWMC pPWM) // pointer to a PWM controller 853 { 854 return pPWM->PWMC_SR; 855 } 856 857 //*---------------------------------------------------------------------------- 858 //* \fn AT91F_PWM_InterruptEnable 859 //* \brief Enable PWM Interrupt 860 //*---------------------------------------------------------------------------- AT91F_PWMC_InterruptEnable(AT91PS_PWMC pPwm,unsigned int flag)861__inline void AT91F_PWMC_InterruptEnable( 862 AT91PS_PWMC pPwm, // \arg pointer to a PWM controller 863 unsigned int flag) // \arg PWM interrupt to be enabled 864 { 865 pPwm->PWMC_IER = flag; 866 } 867 868 //*---------------------------------------------------------------------------- 869 //* \fn AT91F_PWM_InterruptDisable 870 //* \brief Disable PWM Interrupt 871 //*---------------------------------------------------------------------------- AT91F_PWMC_InterruptDisable(AT91PS_PWMC pPwm,unsigned int flag)872__inline void AT91F_PWMC_InterruptDisable( 873 AT91PS_PWMC pPwm, // \arg pointer to a PWM controller 874 unsigned int flag) // \arg PWM interrupt to be disabled 875 { 876 pPwm->PWMC_IDR = flag; 877 } 878 879 //*---------------------------------------------------------------------------- 880 //* \fn AT91F_PWM_GetInterruptMaskStatus 881 //* \brief Return PWM Interrupt Mask Status 882 //*---------------------------------------------------------------------------- AT91F_PWMC_GetInterruptMaskStatus(AT91PS_PWMC pPwm)883__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status 884 AT91PS_PWMC pPwm) // \arg pointer to a PWM controller 885 { 886 return pPwm->PWMC_IMR; 887 } 888 889 //*---------------------------------------------------------------------------- 890 //* \fn AT91F_PWM_IsInterruptMasked 891 //* \brief Test if PWM Interrupt is Masked 892 //*---------------------------------------------------------------------------- AT91F_PWMC_IsInterruptMasked(AT91PS_PWMC pPWM,unsigned int flag)893__inline unsigned int AT91F_PWMC_IsInterruptMasked( 894 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 895 unsigned int flag) // \arg flag to be tested 896 { 897 return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); 898 } 899 900 //*---------------------------------------------------------------------------- 901 //* \fn AT91F_PWM_IsStatusSet 902 //* \brief Test if PWM Interrupt is Set 903 //*---------------------------------------------------------------------------- AT91F_PWMC_IsStatusSet(AT91PS_PWMC pPWM,unsigned int flag)904__inline unsigned int AT91F_PWMC_IsStatusSet( 905 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 906 unsigned int flag) // \arg flag to be tested 907 { 908 return (AT91F_PWMC_GetStatus(pPWM) & flag); 909 } 910 911 //*---------------------------------------------------------------------------- 912 //* \fn AT91F_PWM_CfgChannel 913 //* \brief Test if PWM Interrupt is Set 914 //*---------------------------------------------------------------------------- AT91F_PWMC_CfgChannel(AT91PS_PWMC pPWM,unsigned int channelId,unsigned int mode,unsigned int period,unsigned int duty)915__inline void AT91F_PWMC_CfgChannel( 916 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 917 unsigned int channelId, // \arg PWM channel ID 918 unsigned int mode, // \arg PWM mode 919 unsigned int period, // \arg PWM period 920 unsigned int duty) // \arg PWM duty cycle 921 { 922 pPWM->PWMC_CH[channelId].PWMC_CMR = mode; 923 pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; 924 pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; 925 } 926 927 //*---------------------------------------------------------------------------- 928 //* \fn AT91F_PWM_StartChannel 929 //* \brief Enable channel 930 //*---------------------------------------------------------------------------- AT91F_PWMC_StartChannel(AT91PS_PWMC pPWM,unsigned int flag)931__inline void AT91F_PWMC_StartChannel( 932 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 933 unsigned int flag) // \arg Channels IDs to be enabled 934 { 935 pPWM->PWMC_ENA = flag; 936 } 937 938 //*---------------------------------------------------------------------------- 939 //* \fn AT91F_PWM_StopChannel 940 //* \brief Disable channel 941 //*---------------------------------------------------------------------------- AT91F_PWMC_StopChannel(AT91PS_PWMC pPWM,unsigned int flag)942__inline void AT91F_PWMC_StopChannel( 943 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 944 unsigned int flag) // \arg Channels IDs to be enabled 945 { 946 pPWM->PWMC_DIS = flag; 947 } 948 949 //*---------------------------------------------------------------------------- 950 //* \fn AT91F_PWM_UpdateChannel 951 //* \brief Update Period or Duty Cycle 952 //*---------------------------------------------------------------------------- AT91F_PWMC_UpdateChannel(AT91PS_PWMC pPWM,unsigned int channelId,unsigned int update)953__inline void AT91F_PWMC_UpdateChannel( 954 AT91PS_PWMC pPWM, // \arg pointer to a PWM controller 955 unsigned int channelId, // \arg PWM channel ID 956 unsigned int update) // \arg Channels IDs to be enabled 957 { 958 pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; 959 } 960 961 /* ***************************************************************************** 962 SOFTWARE API FOR TC 963 ***************************************************************************** */ 964 //*---------------------------------------------------------------------------- 965 //* \fn AT91F_TC_InterruptEnable 966 //* \brief Enable TC Interrupt 967 //*---------------------------------------------------------------------------- AT91F_TC_InterruptEnable(AT91PS_TC pTc,unsigned int flag)968__inline void AT91F_TC_InterruptEnable( 969 AT91PS_TC pTc, // \arg pointer to a TC controller 970 unsigned int flag) // \arg TC interrupt to be enabled 971 { 972 pTc->TC_IER = flag; 973 } 974 975 //*---------------------------------------------------------------------------- 976 //* \fn AT91F_TC_InterruptDisable 977 //* \brief Disable TC Interrupt 978 //*---------------------------------------------------------------------------- AT91F_TC_InterruptDisable(AT91PS_TC pTc,unsigned int flag)979__inline void AT91F_TC_InterruptDisable( 980 AT91PS_TC pTc, // \arg pointer to a TC controller 981 unsigned int flag) // \arg TC interrupt to be disabled 982 { 983 pTc->TC_IDR = flag; 984 } 985 986 //*---------------------------------------------------------------------------- 987 //* \fn AT91F_TC_GetInterruptMaskStatus 988 //* \brief Return TC Interrupt Mask Status 989 //*---------------------------------------------------------------------------- AT91F_TC_GetInterruptMaskStatus(AT91PS_TC pTc)990__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status 991 AT91PS_TC pTc) // \arg pointer to a TC controller 992 { 993 return pTc->TC_IMR; 994 } 995 996 //*---------------------------------------------------------------------------- 997 //* \fn AT91F_TC_IsInterruptMasked 998 //* \brief Test if TC Interrupt is Masked 999 //*---------------------------------------------------------------------------- AT91F_TC_IsInterruptMasked(AT91PS_TC pTc,unsigned int flag)1000__inline int AT91F_TC_IsInterruptMasked( 1001 AT91PS_TC pTc, // \arg pointer to a TC controller 1002 unsigned int flag) // \arg flag to be tested 1003 { 1004 return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); 1005 } 1006 1007 /* ***************************************************************************** 1008 SOFTWARE API FOR PMC 1009 ***************************************************************************** */ 1010 //*---------------------------------------------------------------------------- 1011 //* \fn AT91F_PMC_CfgSysClkEnableReg 1012 //* \brief Configure the System Clock Enable Register of the PMC controller 1013 //*---------------------------------------------------------------------------- AT91F_PMC_CfgSysClkEnableReg(AT91PS_PMC pPMC,unsigned int mode)1014__inline void AT91F_PMC_CfgSysClkEnableReg ( 1015 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1016 unsigned int mode) 1017 { 1018 //* Write to the SCER register 1019 pPMC->PMC_SCER = mode; 1020 } 1021 1022 //*---------------------------------------------------------------------------- 1023 //* \fn AT91F_PMC_CfgSysClkDisableReg 1024 //* \brief Configure the System Clock Disable Register of the PMC controller 1025 //*---------------------------------------------------------------------------- AT91F_PMC_CfgSysClkDisableReg(AT91PS_PMC pPMC,unsigned int mode)1026__inline void AT91F_PMC_CfgSysClkDisableReg ( 1027 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1028 unsigned int mode) 1029 { 1030 //* Write to the SCDR register 1031 pPMC->PMC_SCDR = mode; 1032 } 1033 1034 //*---------------------------------------------------------------------------- 1035 //* \fn AT91F_PMC_GetSysClkStatusReg 1036 //* \brief Return the System Clock Status Register of the PMC controller 1037 //*---------------------------------------------------------------------------- AT91F_PMC_GetSysClkStatusReg(AT91PS_PMC pPMC)1038__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( 1039 AT91PS_PMC pPMC // pointer to a CAN controller 1040 ) 1041 { 1042 return pPMC->PMC_SCSR; 1043 } 1044 1045 //*---------------------------------------------------------------------------- 1046 //* \fn AT91F_PMC_EnablePeriphClock 1047 //* \brief Enable peripheral clock 1048 //*---------------------------------------------------------------------------- AT91F_PMC_EnablePeriphClock(AT91PS_PMC pPMC,unsigned int periphIds)1049__inline void AT91F_PMC_EnablePeriphClock ( 1050 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1051 unsigned int periphIds) // \arg IDs of peripherals to enable 1052 { 1053 pPMC->PMC_PCER = periphIds; 1054 } 1055 1056 //*---------------------------------------------------------------------------- 1057 //* \fn AT91F_PMC_DisablePeriphClock 1058 //* \brief Disable peripheral clock 1059 //*---------------------------------------------------------------------------- AT91F_PMC_DisablePeriphClock(AT91PS_PMC pPMC,unsigned int periphIds)1060__inline void AT91F_PMC_DisablePeriphClock ( 1061 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1062 unsigned int periphIds) // \arg IDs of peripherals to enable 1063 { 1064 pPMC->PMC_PCDR = periphIds; 1065 } 1066 1067 //*---------------------------------------------------------------------------- 1068 //* \fn AT91F_PMC_GetPeriphClock 1069 //* \brief Get peripheral clock status 1070 //*---------------------------------------------------------------------------- AT91F_PMC_GetPeriphClock(AT91PS_PMC pPMC)1071__inline unsigned int AT91F_PMC_GetPeriphClock ( 1072 AT91PS_PMC pPMC) // \arg pointer to PMC controller 1073 { 1074 return pPMC->PMC_PCSR; 1075 } 1076 1077 //*---------------------------------------------------------------------------- 1078 //* \fn AT91F_CKGR_CfgMainOscillatorReg 1079 //* \brief Cfg the main oscillator 1080 //*---------------------------------------------------------------------------- AT91F_CKGR_CfgMainOscillatorReg(AT91PS_CKGR pCKGR,unsigned int mode)1081__inline void AT91F_CKGR_CfgMainOscillatorReg ( 1082 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 1083 unsigned int mode) 1084 { 1085 pCKGR->CKGR_MOR = mode; 1086 } 1087 1088 //*---------------------------------------------------------------------------- 1089 //* \fn AT91F_CKGR_GetMainOscillatorReg 1090 //* \brief Cfg the main oscillator 1091 //*---------------------------------------------------------------------------- AT91F_CKGR_GetMainOscillatorReg(AT91PS_CKGR pCKGR)1092__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( 1093 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 1094 { 1095 return pCKGR->CKGR_MOR; 1096 } 1097 1098 //*---------------------------------------------------------------------------- 1099 //* \fn AT91F_CKGR_EnableMainOscillator 1100 //* \brief Enable the main oscillator 1101 //*---------------------------------------------------------------------------- AT91F_CKGR_EnableMainOscillator(AT91PS_CKGR pCKGR)1102__inline void AT91F_CKGR_EnableMainOscillator( 1103 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 1104 { 1105 pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; 1106 } 1107 1108 //*---------------------------------------------------------------------------- 1109 //* \fn AT91F_CKGR_DisableMainOscillator 1110 //* \brief Disable the main oscillator 1111 //*---------------------------------------------------------------------------- AT91F_CKGR_DisableMainOscillator(AT91PS_CKGR pCKGR)1112__inline void AT91F_CKGR_DisableMainOscillator ( 1113 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 1114 { 1115 pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; 1116 } 1117 1118 //*---------------------------------------------------------------------------- 1119 //* \fn AT91F_CKGR_CfgMainOscStartUpTime 1120 //* \brief Cfg MOR Register according to the main osc startup time 1121 //*---------------------------------------------------------------------------- AT91F_CKGR_CfgMainOscStartUpTime(AT91PS_CKGR pCKGR,unsigned int startup_time,unsigned int slowClock)1122__inline void AT91F_CKGR_CfgMainOscStartUpTime ( 1123 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 1124 unsigned int startup_time, // \arg main osc startup time in microsecond (us) 1125 unsigned int slowClock) // \arg slowClock in Hz 1126 { 1127 pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; 1128 pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; 1129 } 1130 1131 //*---------------------------------------------------------------------------- 1132 //* \fn AT91F_CKGR_GetMainClockFreqReg 1133 //* \brief Cfg the main oscillator 1134 //*---------------------------------------------------------------------------- AT91F_CKGR_GetMainClockFreqReg(AT91PS_CKGR pCKGR)1135__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( 1136 AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller 1137 { 1138 return pCKGR->CKGR_MCFR; 1139 } 1140 1141 //*---------------------------------------------------------------------------- 1142 //* \fn AT91F_CKGR_GetMainClock 1143 //* \brief Return Main clock in Hz 1144 //*---------------------------------------------------------------------------- AT91F_CKGR_GetMainClock(AT91PS_CKGR pCKGR,unsigned int slowClock)1145__inline unsigned int AT91F_CKGR_GetMainClock ( 1146 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 1147 unsigned int slowClock) // \arg slowClock in Hz 1148 { 1149 return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; 1150 } 1151 1152 //*---------------------------------------------------------------------------- 1153 //* \fn AT91F_PMC_CfgMCKReg 1154 //* \brief Cfg Master Clock Register 1155 //*---------------------------------------------------------------------------- AT91F_PMC_CfgMCKReg(AT91PS_PMC pPMC,unsigned int mode)1156__inline void AT91F_PMC_CfgMCKReg ( 1157 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1158 unsigned int mode) 1159 { 1160 pPMC->PMC_MCKR = mode; 1161 } 1162 1163 //*---------------------------------------------------------------------------- 1164 //* \fn AT91F_PMC_GetMCKReg 1165 //* \brief Return Master Clock Register 1166 //*---------------------------------------------------------------------------- AT91F_PMC_GetMCKReg(AT91PS_PMC pPMC)1167__inline unsigned int AT91F_PMC_GetMCKReg( 1168 AT91PS_PMC pPMC) // \arg pointer to PMC controller 1169 { 1170 return pPMC->PMC_MCKR; 1171 } 1172 1173 //*------------------------------------------------------------------------------ 1174 //* \fn AT91F_PMC_GetMasterClock 1175 //* \brief Return master clock in Hz which correponds to processor clock for ARM7 1176 //*------------------------------------------------------------------------------ AT91F_PMC_GetMasterClock(AT91PS_PMC pPMC,AT91PS_CKGR pCKGR,unsigned int slowClock)1177__inline unsigned int AT91F_PMC_GetMasterClock ( 1178 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1179 AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller 1180 unsigned int slowClock) // \arg slowClock in Hz 1181 { 1182 unsigned int reg = pPMC->PMC_MCKR; 1183 unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); 1184 unsigned int pllDivider, pllMultiplier; 1185 1186 switch (reg & AT91C_PMC_CSS) { 1187 case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected 1188 return slowClock / prescaler; 1189 case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected 1190 return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; 1191 case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected 1192 reg = pCKGR->CKGR_PLLR; 1193 pllDivider = (reg & AT91C_CKGR_DIV); 1194 pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; 1195 return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; 1196 } 1197 return 0; 1198 } 1199 1200 //*---------------------------------------------------------------------------- 1201 //* \fn AT91F_PMC_EnablePCK 1202 //* \brief Enable peripheral clock 1203 //*---------------------------------------------------------------------------- AT91F_PMC_EnablePCK(AT91PS_PMC pPMC,unsigned int pck,unsigned int mode)1204__inline void AT91F_PMC_EnablePCK ( 1205 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1206 unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 1207 unsigned int mode) 1208 { 1209 pPMC->PMC_PCKR[pck] = mode; 1210 pPMC->PMC_SCER = (1 << pck) << 8; 1211 } 1212 1213 //*---------------------------------------------------------------------------- 1214 //* \fn AT91F_PMC_DisablePCK 1215 //* \brief Enable peripheral clock 1216 //*---------------------------------------------------------------------------- AT91F_PMC_DisablePCK(AT91PS_PMC pPMC,unsigned int pck)1217__inline void AT91F_PMC_DisablePCK ( 1218 AT91PS_PMC pPMC, // \arg pointer to PMC controller 1219 unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 1220 { 1221 pPMC->PMC_SCDR = (1 << pck) << 8; 1222 } 1223 1224 //*---------------------------------------------------------------------------- 1225 //* \fn AT91F_PMC_EnableIt 1226 //* \brief Enable PMC interrupt 1227 //*---------------------------------------------------------------------------- AT91F_PMC_EnableIt(AT91PS_PMC pPMC,unsigned int flag)1228__inline void AT91F_PMC_EnableIt ( 1229 AT91PS_PMC pPMC, // pointer to a PMC controller 1230 unsigned int flag) // IT to be enabled 1231 { 1232 //* Write to the IER register 1233 pPMC->PMC_IER = flag; 1234 } 1235 1236 //*---------------------------------------------------------------------------- 1237 //* \fn AT91F_PMC_DisableIt 1238 //* \brief Disable PMC interrupt 1239 //*---------------------------------------------------------------------------- AT91F_PMC_DisableIt(AT91PS_PMC pPMC,unsigned int flag)1240__inline void AT91F_PMC_DisableIt ( 1241 AT91PS_PMC pPMC, // pointer to a PMC controller 1242 unsigned int flag) // IT to be disabled 1243 { 1244 //* Write to the IDR register 1245 pPMC->PMC_IDR = flag; 1246 } 1247 1248 //*---------------------------------------------------------------------------- 1249 //* \fn AT91F_PMC_GetStatus 1250 //* \brief Return PMC Interrupt Status 1251 //*---------------------------------------------------------------------------- AT91F_PMC_GetStatus(AT91PS_PMC pPMC)1252__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status 1253 AT91PS_PMC pPMC) // pointer to a PMC controller 1254 { 1255 return pPMC->PMC_SR; 1256 } 1257 1258 //*---------------------------------------------------------------------------- 1259 //* \fn AT91F_PMC_GetInterruptMaskStatus 1260 //* \brief Return PMC Interrupt Mask Status 1261 //*---------------------------------------------------------------------------- AT91F_PMC_GetInterruptMaskStatus(AT91PS_PMC pPMC)1262__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status 1263 AT91PS_PMC pPMC) // pointer to a PMC controller 1264 { 1265 return pPMC->PMC_IMR; 1266 } 1267 1268 //*---------------------------------------------------------------------------- 1269 //* \fn AT91F_PMC_IsInterruptMasked 1270 //* \brief Test if PMC Interrupt is Masked 1271 //*---------------------------------------------------------------------------- AT91F_PMC_IsInterruptMasked(AT91PS_PMC pPMC,unsigned int flag)1272__inline unsigned int AT91F_PMC_IsInterruptMasked( 1273 AT91PS_PMC pPMC, // \arg pointer to a PMC controller 1274 unsigned int flag) // \arg flag to be tested 1275 { 1276 return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); 1277 } 1278 1279 //*---------------------------------------------------------------------------- 1280 //* \fn AT91F_PMC_IsStatusSet 1281 //* \brief Test if PMC Status is Set 1282 //*---------------------------------------------------------------------------- AT91F_PMC_IsStatusSet(AT91PS_PMC pPMC,unsigned int flag)1283__inline unsigned int AT91F_PMC_IsStatusSet( 1284 AT91PS_PMC pPMC, // \arg pointer to a PMC controller 1285 unsigned int flag) // \arg flag to be tested 1286 { 1287 return (AT91F_PMC_GetStatus(pPMC) & flag); 1288 }/* ***************************************************************************** 1289 SOFTWARE API FOR ADC 1290 ***************************************************************************** */ 1291 //*---------------------------------------------------------------------------- 1292 //* \fn AT91F_ADC_EnableIt 1293 //* \brief Enable ADC interrupt 1294 //*---------------------------------------------------------------------------- AT91F_ADC_EnableIt(AT91PS_ADC pADC,unsigned int flag)1295__inline void AT91F_ADC_EnableIt ( 1296 AT91PS_ADC pADC, // pointer to a ADC controller 1297 unsigned int flag) // IT to be enabled 1298 { 1299 //* Write to the IER register 1300 pADC->ADC_IER = flag; 1301 } 1302 1303 //*---------------------------------------------------------------------------- 1304 //* \fn AT91F_ADC_DisableIt 1305 //* \brief Disable ADC interrupt 1306 //*---------------------------------------------------------------------------- AT91F_ADC_DisableIt(AT91PS_ADC pADC,unsigned int flag)1307__inline void AT91F_ADC_DisableIt ( 1308 AT91PS_ADC pADC, // pointer to a ADC controller 1309 unsigned int flag) // IT to be disabled 1310 { 1311 //* Write to the IDR register 1312 pADC->ADC_IDR = flag; 1313 } 1314 1315 //*---------------------------------------------------------------------------- 1316 //* \fn AT91F_ADC_GetStatus 1317 //* \brief Return ADC Interrupt Status 1318 //*---------------------------------------------------------------------------- AT91F_ADC_GetStatus(AT91PS_ADC pADC)1319__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status 1320 AT91PS_ADC pADC) // pointer to a ADC controller 1321 { 1322 return pADC->ADC_SR; 1323 } 1324 1325 //*---------------------------------------------------------------------------- 1326 //* \fn AT91F_ADC_GetInterruptMaskStatus 1327 //* \brief Return ADC Interrupt Mask Status 1328 //*---------------------------------------------------------------------------- AT91F_ADC_GetInterruptMaskStatus(AT91PS_ADC pADC)1329__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status 1330 AT91PS_ADC pADC) // pointer to a ADC controller 1331 { 1332 return pADC->ADC_IMR; 1333 } 1334 1335 //*---------------------------------------------------------------------------- 1336 //* \fn AT91F_ADC_IsInterruptMasked 1337 //* \brief Test if ADC Interrupt is Masked 1338 //*---------------------------------------------------------------------------- AT91F_ADC_IsInterruptMasked(AT91PS_ADC pADC,unsigned int flag)1339__inline unsigned int AT91F_ADC_IsInterruptMasked( 1340 AT91PS_ADC pADC, // \arg pointer to a ADC controller 1341 unsigned int flag) // \arg flag to be tested 1342 { 1343 return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); 1344 } 1345 1346 //*---------------------------------------------------------------------------- 1347 //* \fn AT91F_ADC_IsStatusSet 1348 //* \brief Test if ADC Status is Set 1349 //*---------------------------------------------------------------------------- AT91F_ADC_IsStatusSet(AT91PS_ADC pADC,unsigned int flag)1350__inline unsigned int AT91F_ADC_IsStatusSet( 1351 AT91PS_ADC pADC, // \arg pointer to a ADC controller 1352 unsigned int flag) // \arg flag to be tested 1353 { 1354 return (AT91F_ADC_GetStatus(pADC) & flag); 1355 } 1356 1357 //*---------------------------------------------------------------------------- 1358 //* \fn AT91F_ADC_CfgModeReg 1359 //* \brief Configure the Mode Register of the ADC controller 1360 //*---------------------------------------------------------------------------- AT91F_ADC_CfgModeReg(AT91PS_ADC pADC,unsigned int mode)1361__inline void AT91F_ADC_CfgModeReg ( 1362 AT91PS_ADC pADC, // pointer to a ADC controller 1363 unsigned int mode) // mode register 1364 { 1365 //* Write to the MR register 1366 pADC->ADC_MR = mode; 1367 } 1368 1369 //*---------------------------------------------------------------------------- 1370 //* \fn AT91F_ADC_GetModeReg 1371 //* \brief Return the Mode Register of the ADC controller value 1372 //*---------------------------------------------------------------------------- AT91F_ADC_GetModeReg(AT91PS_ADC pADC)1373__inline unsigned int AT91F_ADC_GetModeReg ( 1374 AT91PS_ADC pADC // pointer to a ADC controller 1375 ) 1376 { 1377 return pADC->ADC_MR; 1378 } 1379 1380 //*---------------------------------------------------------------------------- 1381 //* \fn AT91F_ADC_CfgTimings 1382 //* \brief Configure the different necessary timings of the ADC controller 1383 //*---------------------------------------------------------------------------- AT91F_ADC_CfgTimings(AT91PS_ADC pADC,unsigned int mck_clock,unsigned int adc_clock,unsigned int startup_time,unsigned int sample_and_hold_time)1384__inline void AT91F_ADC_CfgTimings ( 1385 AT91PS_ADC pADC, // pointer to a ADC controller 1386 unsigned int mck_clock, // in MHz 1387 unsigned int adc_clock, // in MHz 1388 unsigned int startup_time, // in us 1389 unsigned int sample_and_hold_time) // in ns 1390 { 1391 unsigned int prescal,startup,shtim; 1392 1393 prescal = mck_clock/(2*adc_clock) - 1; 1394 startup = adc_clock*startup_time/8 - 1; 1395 shtim = adc_clock*sample_and_hold_time/1000 - 1; 1396 1397 //* Write to the MR register 1398 pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); 1399 } 1400 1401 //*---------------------------------------------------------------------------- 1402 //* \fn AT91F_ADC_EnableChannel 1403 //* \brief Return ADC Timer Register Value 1404 //*---------------------------------------------------------------------------- AT91F_ADC_EnableChannel(AT91PS_ADC pADC,unsigned int channel)1405__inline void AT91F_ADC_EnableChannel ( 1406 AT91PS_ADC pADC, // pointer to a ADC controller 1407 unsigned int channel) // mode register 1408 { 1409 //* Write to the CHER register 1410 pADC->ADC_CHER = channel; 1411 } 1412 1413 //*---------------------------------------------------------------------------- 1414 //* \fn AT91F_ADC_DisableChannel 1415 //* \brief Return ADC Timer Register Value 1416 //*---------------------------------------------------------------------------- AT91F_ADC_DisableChannel(AT91PS_ADC pADC,unsigned int channel)1417__inline void AT91F_ADC_DisableChannel ( 1418 AT91PS_ADC pADC, // pointer to a ADC controller 1419 unsigned int channel) // mode register 1420 { 1421 //* Write to the CHDR register 1422 pADC->ADC_CHDR = channel; 1423 } 1424 1425 //*---------------------------------------------------------------------------- 1426 //* \fn AT91F_ADC_GetChannelStatus 1427 //* \brief Return ADC Timer Register Value 1428 //*---------------------------------------------------------------------------- AT91F_ADC_GetChannelStatus(AT91PS_ADC pADC)1429__inline unsigned int AT91F_ADC_GetChannelStatus ( 1430 AT91PS_ADC pADC // pointer to a ADC controller 1431 ) 1432 { 1433 return pADC->ADC_CHSR; 1434 } 1435 1436 //*---------------------------------------------------------------------------- 1437 //* \fn AT91F_ADC_StartConversion 1438 //* \brief Software request for a analog to digital conversion 1439 //*---------------------------------------------------------------------------- AT91F_ADC_StartConversion(AT91PS_ADC pADC)1440__inline void AT91F_ADC_StartConversion ( 1441 AT91PS_ADC pADC // pointer to a ADC controller 1442 ) 1443 { 1444 pADC->ADC_CR = AT91C_ADC_START; 1445 } 1446 1447 //*---------------------------------------------------------------------------- 1448 //* \fn AT91F_ADC_SoftReset 1449 //* \brief Software reset 1450 //*---------------------------------------------------------------------------- AT91F_ADC_SoftReset(AT91PS_ADC pADC)1451__inline void AT91F_ADC_SoftReset ( 1452 AT91PS_ADC pADC // pointer to a ADC controller 1453 ) 1454 { 1455 pADC->ADC_CR = AT91C_ADC_SWRST; 1456 } 1457 1458 //*---------------------------------------------------------------------------- 1459 //* \fn AT91F_ADC_GetLastConvertedData 1460 //* \brief Return the Last Converted Data 1461 //*---------------------------------------------------------------------------- AT91F_ADC_GetLastConvertedData(AT91PS_ADC pADC)1462__inline unsigned int AT91F_ADC_GetLastConvertedData ( 1463 AT91PS_ADC pADC // pointer to a ADC controller 1464 ) 1465 { 1466 return pADC->ADC_LCDR; 1467 } 1468 1469 //*---------------------------------------------------------------------------- 1470 //* \fn AT91F_ADC_GetConvertedDataCH0 1471 //* \brief Return the Channel 0 Converted Data 1472 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH0(AT91PS_ADC pADC)1473__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( 1474 AT91PS_ADC pADC // pointer to a ADC controller 1475 ) 1476 { 1477 return pADC->ADC_CDR0; 1478 } 1479 1480 //*---------------------------------------------------------------------------- 1481 //* \fn AT91F_ADC_GetConvertedDataCH1 1482 //* \brief Return the Channel 1 Converted Data 1483 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH1(AT91PS_ADC pADC)1484__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( 1485 AT91PS_ADC pADC // pointer to a ADC controller 1486 ) 1487 { 1488 return pADC->ADC_CDR1; 1489 } 1490 1491 //*---------------------------------------------------------------------------- 1492 //* \fn AT91F_ADC_GetConvertedDataCH2 1493 //* \brief Return the Channel 2 Converted Data 1494 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH2(AT91PS_ADC pADC)1495__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( 1496 AT91PS_ADC pADC // pointer to a ADC controller 1497 ) 1498 { 1499 return pADC->ADC_CDR2; 1500 } 1501 1502 //*---------------------------------------------------------------------------- 1503 //* \fn AT91F_ADC_GetConvertedDataCH3 1504 //* \brief Return the Channel 3 Converted Data 1505 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH3(AT91PS_ADC pADC)1506__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( 1507 AT91PS_ADC pADC // pointer to a ADC controller 1508 ) 1509 { 1510 return pADC->ADC_CDR3; 1511 } 1512 1513 //*---------------------------------------------------------------------------- 1514 //* \fn AT91F_ADC_GetConvertedDataCH4 1515 //* \brief Return the Channel 4 Converted Data 1516 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH4(AT91PS_ADC pADC)1517__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( 1518 AT91PS_ADC pADC // pointer to a ADC controller 1519 ) 1520 { 1521 return pADC->ADC_CDR4; 1522 } 1523 1524 //*---------------------------------------------------------------------------- 1525 //* \fn AT91F_ADC_GetConvertedDataCH5 1526 //* \brief Return the Channel 5 Converted Data 1527 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH5(AT91PS_ADC pADC)1528__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( 1529 AT91PS_ADC pADC // pointer to a ADC controller 1530 ) 1531 { 1532 return pADC->ADC_CDR5; 1533 } 1534 1535 //*---------------------------------------------------------------------------- 1536 //* \fn AT91F_ADC_GetConvertedDataCH6 1537 //* \brief Return the Channel 6 Converted Data 1538 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH6(AT91PS_ADC pADC)1539__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( 1540 AT91PS_ADC pADC // pointer to a ADC controller 1541 ) 1542 { 1543 return pADC->ADC_CDR6; 1544 } 1545 1546 //*---------------------------------------------------------------------------- 1547 //* \fn AT91F_ADC_GetConvertedDataCH7 1548 //* \brief Return the Channel 7 Converted Data 1549 //*---------------------------------------------------------------------------- AT91F_ADC_GetConvertedDataCH7(AT91PS_ADC pADC)1550__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( 1551 AT91PS_ADC pADC // pointer to a ADC controller 1552 ) 1553 { 1554 return pADC->ADC_CDR7; 1555 } 1556 1557 /* ***************************************************************************** 1558 SOFTWARE API FOR PIO 1559 ***************************************************************************** */ 1560 //*---------------------------------------------------------------------------- 1561 //* \fn AT91F_PIO_CfgPeriph 1562 //* \brief Enable pins to be drived by peripheral 1563 //*---------------------------------------------------------------------------- AT91F_PIO_CfgPeriph(AT91PS_PIO pPio,unsigned int periphAEnable,unsigned int periphBEnable)1564__inline void AT91F_PIO_CfgPeriph( 1565 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1566 unsigned int periphAEnable, // \arg PERIPH A to enable 1567 unsigned int periphBEnable) // \arg PERIPH B to enable 1568 1569 { 1570 pPio->PIO_ASR = periphAEnable; 1571 pPio->PIO_BSR = periphBEnable; 1572 pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode 1573 } 1574 1575 //*---------------------------------------------------------------------------- 1576 //* \fn AT91F_PIO_CfgOutput 1577 //* \brief Enable PIO in output mode 1578 //*---------------------------------------------------------------------------- AT91F_PIO_CfgOutput(AT91PS_PIO pPio,unsigned int pioEnable)1579__inline void AT91F_PIO_CfgOutput( 1580 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1581 unsigned int pioEnable) // \arg PIO to be enabled 1582 { 1583 pPio->PIO_PER = pioEnable; // Set in PIO mode 1584 pPio->PIO_OER = pioEnable; // Configure in Output 1585 } 1586 1587 //*---------------------------------------------------------------------------- 1588 //* \fn AT91F_PIO_CfgInput 1589 //* \brief Enable PIO in input mode 1590 //*---------------------------------------------------------------------------- AT91F_PIO_CfgInput(AT91PS_PIO pPio,unsigned int inputEnable)1591__inline void AT91F_PIO_CfgInput( 1592 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1593 unsigned int inputEnable) // \arg PIO to be enabled 1594 { 1595 // Disable output 1596 pPio->PIO_ODR = inputEnable; 1597 pPio->PIO_PER = inputEnable; 1598 } 1599 1600 //*---------------------------------------------------------------------------- 1601 //* \fn AT91F_PIO_CfgOpendrain 1602 //* \brief Configure PIO in open drain 1603 //*---------------------------------------------------------------------------- AT91F_PIO_CfgOpendrain(AT91PS_PIO pPio,unsigned int multiDrvEnable)1604__inline void AT91F_PIO_CfgOpendrain( 1605 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1606 unsigned int multiDrvEnable) // \arg pio to be configured in open drain 1607 { 1608 // Configure the multi-drive option 1609 pPio->PIO_MDDR = ~multiDrvEnable; 1610 pPio->PIO_MDER = multiDrvEnable; 1611 } 1612 1613 //*---------------------------------------------------------------------------- 1614 //* \fn AT91F_PIO_CfgPullup 1615 //* \brief Enable pullup on PIO 1616 //*---------------------------------------------------------------------------- AT91F_PIO_CfgPullup(AT91PS_PIO pPio,unsigned int pullupEnable)1617__inline void AT91F_PIO_CfgPullup( 1618 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1619 unsigned int pullupEnable) // \arg enable pullup on PIO 1620 { 1621 // Connect or not Pullup 1622 pPio->PIO_PPUDR = ~pullupEnable; 1623 pPio->PIO_PPUER = pullupEnable; 1624 } 1625 1626 //*---------------------------------------------------------------------------- 1627 //* \fn AT91F_PIO_CfgDirectDrive 1628 //* \brief Enable direct drive on PIO 1629 //*---------------------------------------------------------------------------- AT91F_PIO_CfgDirectDrive(AT91PS_PIO pPio,unsigned int directDrive)1630__inline void AT91F_PIO_CfgDirectDrive( 1631 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1632 unsigned int directDrive) // \arg PIO to be configured with direct drive 1633 1634 { 1635 // Configure the Direct Drive 1636 pPio->PIO_OWDR = ~directDrive; 1637 pPio->PIO_OWER = directDrive; 1638 } 1639 1640 //*---------------------------------------------------------------------------- 1641 //* \fn AT91F_PIO_CfgInputFilter 1642 //* \brief Enable input filter on input PIO 1643 //*---------------------------------------------------------------------------- AT91F_PIO_CfgInputFilter(AT91PS_PIO pPio,unsigned int inputFilter)1644__inline void AT91F_PIO_CfgInputFilter( 1645 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1646 unsigned int inputFilter) // \arg PIO to be configured with input filter 1647 1648 { 1649 // Configure the Direct Drive 1650 pPio->PIO_IFDR = ~inputFilter; 1651 pPio->PIO_IFER = inputFilter; 1652 } 1653 1654 //*---------------------------------------------------------------------------- 1655 //* \fn AT91F_PIO_GetInput 1656 //* \brief Return PIO input value 1657 //*---------------------------------------------------------------------------- AT91F_PIO_GetInput(AT91PS_PIO pPio)1658__inline unsigned int AT91F_PIO_GetInput( // \return PIO input 1659 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1660 { 1661 return pPio->PIO_PDSR; 1662 } 1663 1664 //*---------------------------------------------------------------------------- 1665 //* \fn AT91F_PIO_IsInputSet 1666 //* \brief Test if PIO is input flag is active 1667 //*---------------------------------------------------------------------------- AT91F_PIO_IsInputSet(AT91PS_PIO pPio,unsigned int flag)1668__inline int AT91F_PIO_IsInputSet( 1669 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1670 unsigned int flag) // \arg flag to be tested 1671 { 1672 return (AT91F_PIO_GetInput(pPio) & flag); 1673 } 1674 1675 1676 //*---------------------------------------------------------------------------- 1677 //* \fn AT91F_PIO_SetOutput 1678 //* \brief Set to 1 output PIO 1679 //*---------------------------------------------------------------------------- AT91F_PIO_SetOutput(AT91PS_PIO pPio,unsigned int flag)1680__inline void AT91F_PIO_SetOutput( 1681 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1682 unsigned int flag) // \arg output to be set 1683 { 1684 pPio->PIO_SODR = flag; 1685 } 1686 1687 //*---------------------------------------------------------------------------- 1688 //* \fn AT91F_PIO_ClearOutput 1689 //* \brief Set to 0 output PIO 1690 //*---------------------------------------------------------------------------- AT91F_PIO_ClearOutput(AT91PS_PIO pPio,unsigned int flag)1691__inline void AT91F_PIO_ClearOutput( 1692 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1693 unsigned int flag) // \arg output to be cleared 1694 { 1695 pPio->PIO_CODR = flag; 1696 } 1697 1698 //*---------------------------------------------------------------------------- 1699 //* \fn AT91F_PIO_ForceOutput 1700 //* \brief Force output when Direct drive option is enabled 1701 //*---------------------------------------------------------------------------- AT91F_PIO_ForceOutput(AT91PS_PIO pPio,unsigned int flag)1702__inline void AT91F_PIO_ForceOutput( 1703 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1704 unsigned int flag) // \arg output to be forced 1705 { 1706 pPio->PIO_ODSR = flag; 1707 } 1708 1709 //*---------------------------------------------------------------------------- 1710 //* \fn AT91F_PIO_Enable 1711 //* \brief Enable PIO 1712 //*---------------------------------------------------------------------------- AT91F_PIO_Enable(AT91PS_PIO pPio,unsigned int flag)1713__inline void AT91F_PIO_Enable( 1714 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1715 unsigned int flag) // \arg pio to be enabled 1716 { 1717 pPio->PIO_PER = flag; 1718 } 1719 1720 //*---------------------------------------------------------------------------- 1721 //* \fn AT91F_PIO_Disable 1722 //* \brief Disable PIO 1723 //*---------------------------------------------------------------------------- AT91F_PIO_Disable(AT91PS_PIO pPio,unsigned int flag)1724__inline void AT91F_PIO_Disable( 1725 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1726 unsigned int flag) // \arg pio to be disabled 1727 { 1728 pPio->PIO_PDR = flag; 1729 } 1730 1731 //*---------------------------------------------------------------------------- 1732 //* \fn AT91F_PIO_GetStatus 1733 //* \brief Return PIO Status 1734 //*---------------------------------------------------------------------------- AT91F_PIO_GetStatus(AT91PS_PIO pPio)1735__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status 1736 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1737 { 1738 return pPio->PIO_PSR; 1739 } 1740 1741 //*---------------------------------------------------------------------------- 1742 //* \fn AT91F_PIO_IsSet 1743 //* \brief Test if PIO is Set 1744 //*---------------------------------------------------------------------------- AT91F_PIO_IsSet(AT91PS_PIO pPio,unsigned int flag)1745__inline int AT91F_PIO_IsSet( 1746 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1747 unsigned int flag) // \arg flag to be tested 1748 { 1749 return (AT91F_PIO_GetStatus(pPio) & flag); 1750 } 1751 1752 //*---------------------------------------------------------------------------- 1753 //* \fn AT91F_PIO_OutputEnable 1754 //* \brief Output Enable PIO 1755 //*---------------------------------------------------------------------------- AT91F_PIO_OutputEnable(AT91PS_PIO pPio,unsigned int flag)1756__inline void AT91F_PIO_OutputEnable( 1757 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1758 unsigned int flag) // \arg pio output to be enabled 1759 { 1760 pPio->PIO_OER = flag; 1761 } 1762 1763 //*---------------------------------------------------------------------------- 1764 //* \fn AT91F_PIO_OutputDisable 1765 //* \brief Output Enable PIO 1766 //*---------------------------------------------------------------------------- AT91F_PIO_OutputDisable(AT91PS_PIO pPio,unsigned int flag)1767__inline void AT91F_PIO_OutputDisable( 1768 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1769 unsigned int flag) // \arg pio output to be disabled 1770 { 1771 pPio->PIO_ODR = flag; 1772 } 1773 1774 //*---------------------------------------------------------------------------- 1775 //* \fn AT91F_PIO_GetOutputStatus 1776 //* \brief Return PIO Output Status 1777 //*---------------------------------------------------------------------------- AT91F_PIO_GetOutputStatus(AT91PS_PIO pPio)1778__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status 1779 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1780 { 1781 return pPio->PIO_OSR; 1782 } 1783 1784 //*---------------------------------------------------------------------------- 1785 //* \fn AT91F_PIO_IsOuputSet 1786 //* \brief Test if PIO Output is Set 1787 //*---------------------------------------------------------------------------- AT91F_PIO_IsOutputSet(AT91PS_PIO pPio,unsigned int flag)1788__inline int AT91F_PIO_IsOutputSet( 1789 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1790 unsigned int flag) // \arg flag to be tested 1791 { 1792 return (AT91F_PIO_GetOutputStatus(pPio) & flag); 1793 } 1794 1795 //*---------------------------------------------------------------------------- 1796 //* \fn AT91F_PIO_InputFilterEnable 1797 //* \brief Input Filter Enable PIO 1798 //*---------------------------------------------------------------------------- AT91F_PIO_InputFilterEnable(AT91PS_PIO pPio,unsigned int flag)1799__inline void AT91F_PIO_InputFilterEnable( 1800 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1801 unsigned int flag) // \arg pio input filter to be enabled 1802 { 1803 pPio->PIO_IFER = flag; 1804 } 1805 1806 //*---------------------------------------------------------------------------- 1807 //* \fn AT91F_PIO_InputFilterDisable 1808 //* \brief Input Filter Disable PIO 1809 //*---------------------------------------------------------------------------- AT91F_PIO_InputFilterDisable(AT91PS_PIO pPio,unsigned int flag)1810__inline void AT91F_PIO_InputFilterDisable( 1811 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1812 unsigned int flag) // \arg pio input filter to be disabled 1813 { 1814 pPio->PIO_IFDR = flag; 1815 } 1816 1817 //*---------------------------------------------------------------------------- 1818 //* \fn AT91F_PIO_GetInputFilterStatus 1819 //* \brief Return PIO Input Filter Status 1820 //*---------------------------------------------------------------------------- AT91F_PIO_GetInputFilterStatus(AT91PS_PIO pPio)1821__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status 1822 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1823 { 1824 return pPio->PIO_IFSR; 1825 } 1826 1827 //*---------------------------------------------------------------------------- 1828 //* \fn AT91F_PIO_IsInputFilterSet 1829 //* \brief Test if PIO Input filter is Set 1830 //*---------------------------------------------------------------------------- AT91F_PIO_IsInputFilterSet(AT91PS_PIO pPio,unsigned int flag)1831__inline int AT91F_PIO_IsInputFilterSet( 1832 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1833 unsigned int flag) // \arg flag to be tested 1834 { 1835 return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); 1836 } 1837 1838 //*---------------------------------------------------------------------------- 1839 //* \fn AT91F_PIO_GetOutputDataStatus 1840 //* \brief Return PIO Output Data Status 1841 //*---------------------------------------------------------------------------- AT91F_PIO_GetOutputDataStatus(AT91PS_PIO pPio)1842__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 1843 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1844 { 1845 return pPio->PIO_ODSR; 1846 } 1847 1848 //*---------------------------------------------------------------------------- 1849 //* \fn AT91F_PIO_InterruptEnable 1850 //* \brief Enable PIO Interrupt 1851 //*---------------------------------------------------------------------------- AT91F_PIO_InterruptEnable(AT91PS_PIO pPio,unsigned int flag)1852__inline void AT91F_PIO_InterruptEnable( 1853 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1854 unsigned int flag) // \arg pio interrupt to be enabled 1855 { 1856 pPio->PIO_IER = flag; 1857 } 1858 1859 //*---------------------------------------------------------------------------- 1860 //* \fn AT91F_PIO_InterruptDisable 1861 //* \brief Disable PIO Interrupt 1862 //*---------------------------------------------------------------------------- AT91F_PIO_InterruptDisable(AT91PS_PIO pPio,unsigned int flag)1863__inline void AT91F_PIO_InterruptDisable( 1864 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1865 unsigned int flag) // \arg pio interrupt to be disabled 1866 { 1867 pPio->PIO_IDR = flag; 1868 } 1869 1870 //*---------------------------------------------------------------------------- 1871 //* \fn AT91F_PIO_GetInterruptMaskStatus 1872 //* \brief Return PIO Interrupt Mask Status 1873 //*---------------------------------------------------------------------------- AT91F_PIO_GetInterruptMaskStatus(AT91PS_PIO pPio)1874__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status 1875 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1876 { 1877 return pPio->PIO_IMR; 1878 } 1879 1880 //*---------------------------------------------------------------------------- 1881 //* \fn AT91F_PIO_GetInterruptStatus 1882 //* \brief Return PIO Interrupt Status 1883 //*---------------------------------------------------------------------------- AT91F_PIO_GetInterruptStatus(AT91PS_PIO pPio)1884__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status 1885 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1886 { 1887 return pPio->PIO_ISR; 1888 } 1889 1890 //*---------------------------------------------------------------------------- 1891 //* \fn AT91F_PIO_IsInterruptMasked 1892 //* \brief Test if PIO Interrupt is Masked 1893 //*---------------------------------------------------------------------------- AT91F_PIO_IsInterruptMasked(AT91PS_PIO pPio,unsigned int flag)1894__inline int AT91F_PIO_IsInterruptMasked( 1895 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1896 unsigned int flag) // \arg flag to be tested 1897 { 1898 return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); 1899 } 1900 1901 //*---------------------------------------------------------------------------- 1902 //* \fn AT91F_PIO_IsInterruptSet 1903 //* \brief Test if PIO Interrupt is Set 1904 //*---------------------------------------------------------------------------- AT91F_PIO_IsInterruptSet(AT91PS_PIO pPio,unsigned int flag)1905__inline int AT91F_PIO_IsInterruptSet( 1906 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1907 unsigned int flag) // \arg flag to be tested 1908 { 1909 return (AT91F_PIO_GetInterruptStatus(pPio) & flag); 1910 } 1911 1912 //*---------------------------------------------------------------------------- 1913 //* \fn AT91F_PIO_MultiDriverEnable 1914 //* \brief Multi Driver Enable PIO 1915 //*---------------------------------------------------------------------------- AT91F_PIO_MultiDriverEnable(AT91PS_PIO pPio,unsigned int flag)1916__inline void AT91F_PIO_MultiDriverEnable( 1917 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1918 unsigned int flag) // \arg pio to be enabled 1919 { 1920 pPio->PIO_MDER = flag; 1921 } 1922 1923 //*---------------------------------------------------------------------------- 1924 //* \fn AT91F_PIO_MultiDriverDisable 1925 //* \brief Multi Driver Disable PIO 1926 //*---------------------------------------------------------------------------- AT91F_PIO_MultiDriverDisable(AT91PS_PIO pPio,unsigned int flag)1927__inline void AT91F_PIO_MultiDriverDisable( 1928 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1929 unsigned int flag) // \arg pio to be disabled 1930 { 1931 pPio->PIO_MDDR = flag; 1932 } 1933 1934 //*---------------------------------------------------------------------------- 1935 //* \fn AT91F_PIO_GetMultiDriverStatus 1936 //* \brief Return PIO Multi Driver Status 1937 //*---------------------------------------------------------------------------- AT91F_PIO_GetMultiDriverStatus(AT91PS_PIO pPio)1938__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status 1939 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1940 { 1941 return pPio->PIO_MDSR; 1942 } 1943 1944 //*---------------------------------------------------------------------------- 1945 //* \fn AT91F_PIO_IsMultiDriverSet 1946 //* \brief Test if PIO MultiDriver is Set 1947 //*---------------------------------------------------------------------------- AT91F_PIO_IsMultiDriverSet(AT91PS_PIO pPio,unsigned int flag)1948__inline int AT91F_PIO_IsMultiDriverSet( 1949 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1950 unsigned int flag) // \arg flag to be tested 1951 { 1952 return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); 1953 } 1954 1955 //*---------------------------------------------------------------------------- 1956 //* \fn AT91F_PIO_A_RegisterSelection 1957 //* \brief PIO A Register Selection 1958 //*---------------------------------------------------------------------------- AT91F_PIO_A_RegisterSelection(AT91PS_PIO pPio,unsigned int flag)1959__inline void AT91F_PIO_A_RegisterSelection( 1960 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1961 unsigned int flag) // \arg pio A register selection 1962 { 1963 pPio->PIO_ASR = flag; 1964 } 1965 1966 //*---------------------------------------------------------------------------- 1967 //* \fn AT91F_PIO_B_RegisterSelection 1968 //* \brief PIO B Register Selection 1969 //*---------------------------------------------------------------------------- AT91F_PIO_B_RegisterSelection(AT91PS_PIO pPio,unsigned int flag)1970__inline void AT91F_PIO_B_RegisterSelection( 1971 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1972 unsigned int flag) // \arg pio B register selection 1973 { 1974 pPio->PIO_BSR = flag; 1975 } 1976 1977 //*---------------------------------------------------------------------------- 1978 //* \fn AT91F_PIO_Get_AB_RegisterStatus 1979 //* \brief Return PIO Interrupt Status 1980 //*---------------------------------------------------------------------------- AT91F_PIO_Get_AB_RegisterStatus(AT91PS_PIO pPio)1981__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status 1982 AT91PS_PIO pPio) // \arg pointer to a PIO controller 1983 { 1984 return pPio->PIO_ABSR; 1985 } 1986 1987 //*---------------------------------------------------------------------------- 1988 //* \fn AT91F_PIO_IsAB_RegisterSet 1989 //* \brief Test if PIO AB Register is Set 1990 //*---------------------------------------------------------------------------- AT91F_PIO_IsAB_RegisterSet(AT91PS_PIO pPio,unsigned int flag)1991__inline int AT91F_PIO_IsAB_RegisterSet( 1992 AT91PS_PIO pPio, // \arg pointer to a PIO controller 1993 unsigned int flag) // \arg flag to be tested 1994 { 1995 return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); 1996 } 1997 1998 //*---------------------------------------------------------------------------- 1999 //* \fn AT91F_PIO_OutputWriteEnable 2000 //* \brief Output Write Enable PIO 2001 //*---------------------------------------------------------------------------- AT91F_PIO_OutputWriteEnable(AT91PS_PIO pPio,unsigned int flag)2002__inline void AT91F_PIO_OutputWriteEnable( 2003 AT91PS_PIO pPio, // \arg pointer to a PIO controller 2004 unsigned int flag) // \arg pio output write to be enabled 2005 { 2006 pPio->PIO_OWER = flag; 2007 } 2008 2009 //*---------------------------------------------------------------------------- 2010 //* \fn AT91F_PIO_OutputWriteDisable 2011 //* \brief Output Write Disable PIO 2012 //*---------------------------------------------------------------------------- AT91F_PIO_OutputWriteDisable(AT91PS_PIO pPio,unsigned int flag)2013__inline void AT91F_PIO_OutputWriteDisable( 2014 AT91PS_PIO pPio, // \arg pointer to a PIO controller 2015 unsigned int flag) // \arg pio output write to be disabled 2016 { 2017 pPio->PIO_OWDR = flag; 2018 } 2019 2020 //*---------------------------------------------------------------------------- 2021 //* \fn AT91F_PIO_GetOutputWriteStatus 2022 //* \brief Return PIO Output Write Status 2023 //*---------------------------------------------------------------------------- AT91F_PIO_GetOutputWriteStatus(AT91PS_PIO pPio)2024__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status 2025 AT91PS_PIO pPio) // \arg pointer to a PIO controller 2026 { 2027 return pPio->PIO_OWSR; 2028 } 2029 2030 //*---------------------------------------------------------------------------- 2031 //* \fn AT91F_PIO_IsOutputWriteSet 2032 //* \brief Test if PIO OutputWrite is Set 2033 //*---------------------------------------------------------------------------- AT91F_PIO_IsOutputWriteSet(AT91PS_PIO pPio,unsigned int flag)2034__inline int AT91F_PIO_IsOutputWriteSet( 2035 AT91PS_PIO pPio, // \arg pointer to a PIO controller 2036 unsigned int flag) // \arg flag to be tested 2037 { 2038 return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); 2039 } 2040 2041 //*---------------------------------------------------------------------------- 2042 //* \fn AT91F_PIO_GetCfgPullup 2043 //* \brief Return PIO Configuration Pullup 2044 //*---------------------------------------------------------------------------- AT91F_PIO_GetCfgPullup(AT91PS_PIO pPio)2045__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 2046 AT91PS_PIO pPio) // \arg pointer to a PIO controller 2047 { 2048 return pPio->PIO_PPUSR; 2049 } 2050 2051 //*---------------------------------------------------------------------------- 2052 //* \fn AT91F_PIO_IsOutputDataStatusSet 2053 //* \brief Test if PIO Output Data Status is Set 2054 //*---------------------------------------------------------------------------- AT91F_PIO_IsOutputDataStatusSet(AT91PS_PIO pPio,unsigned int flag)2055__inline int AT91F_PIO_IsOutputDataStatusSet( 2056 AT91PS_PIO pPio, // \arg pointer to a PIO controller 2057 unsigned int flag) // \arg flag to be tested 2058 { 2059 return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); 2060 } 2061 2062 //*---------------------------------------------------------------------------- 2063 //* \fn AT91F_PIO_IsCfgPullupStatusSet 2064 //* \brief Test if PIO Configuration Pullup Status is Set 2065 //*---------------------------------------------------------------------------- AT91F_PIO_IsCfgPullupStatusSet(AT91PS_PIO pPio,unsigned int flag)2066__inline int AT91F_PIO_IsCfgPullupStatusSet( 2067 AT91PS_PIO pPio, // \arg pointer to a PIO controller 2068 unsigned int flag) // \arg flag to be tested 2069 { 2070 return (~AT91F_PIO_GetCfgPullup(pPio) & flag); 2071 } 2072 2073 /* ***************************************************************************** 2074 SOFTWARE API FOR TWI 2075 ***************************************************************************** */ 2076 //*---------------------------------------------------------------------------- 2077 //* \fn AT91F_TWI_EnableIt 2078 //* \brief Enable TWI IT 2079 //*---------------------------------------------------------------------------- AT91F_TWI_EnableIt(AT91PS_TWI pTWI,unsigned int flag)2080__inline void AT91F_TWI_EnableIt ( 2081 AT91PS_TWI pTWI, // \arg pointer to a TWI controller 2082 unsigned int flag) // \arg IT to be enabled 2083 { 2084 //* Write to the IER register 2085 pTWI->TWI_IER = flag; 2086 } 2087 2088 //*---------------------------------------------------------------------------- 2089 //* \fn AT91F_TWI_DisableIt 2090 //* \brief Disable TWI IT 2091 //*---------------------------------------------------------------------------- AT91F_TWI_DisableIt(AT91PS_TWI pTWI,unsigned int flag)2092__inline void AT91F_TWI_DisableIt ( 2093 AT91PS_TWI pTWI, // \arg pointer to a TWI controller 2094 unsigned int flag) // \arg IT to be disabled 2095 { 2096 //* Write to the IDR register 2097 pTWI->TWI_IDR = flag; 2098 } 2099 2100 //*---------------------------------------------------------------------------- 2101 //* \fn AT91F_TWI_Configure 2102 //* \brief Configure TWI in master mode 2103 //*---------------------------------------------------------------------------- AT91F_TWI_Configure(AT91PS_TWI pTWI)2104__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller 2105 { 2106 //* Disable interrupts 2107 pTWI->TWI_IDR = (unsigned int) -1; 2108 2109 //* Reset peripheral 2110 pTWI->TWI_CR = AT91C_TWI_SWRST; 2111 2112 //* Set Master mode 2113 pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; 2114 2115 } 2116 2117 //*---------------------------------------------------------------------------- 2118 //* \fn AT91F_TWI_GetInterruptMaskStatus 2119 //* \brief Return TWI Interrupt Mask Status 2120 //*---------------------------------------------------------------------------- AT91F_TWI_GetInterruptMaskStatus(AT91PS_TWI pTwi)2121__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status 2122 AT91PS_TWI pTwi) // \arg pointer to a TWI controller 2123 { 2124 return pTwi->TWI_IMR; 2125 } 2126 2127 //*---------------------------------------------------------------------------- 2128 //* \fn AT91F_TWI_IsInterruptMasked 2129 //* \brief Test if TWI Interrupt is Masked 2130 //*---------------------------------------------------------------------------- AT91F_TWI_IsInterruptMasked(AT91PS_TWI pTwi,unsigned int flag)2131__inline int AT91F_TWI_IsInterruptMasked( 2132 AT91PS_TWI pTwi, // \arg pointer to a TWI controller 2133 unsigned int flag) // \arg flag to be tested 2134 { 2135 return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); 2136 } 2137 2138 /* ***************************************************************************** 2139 SOFTWARE API FOR USART 2140 ***************************************************************************** */ 2141 //*---------------------------------------------------------------------------- 2142 //* \fn AT91F_US_Baudrate 2143 //* \brief Calculate the baudrate 2144 //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity 2145 #define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ 2146 AT91C_US_NBSTOP_1_BIT + \ 2147 AT91C_US_PAR_NONE + \ 2148 AT91C_US_CHRL_8_BITS + \ 2149 AT91C_US_CLKS_CLOCK ) 2150 2151 //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity 2152 #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ 2153 AT91C_US_NBSTOP_1_BIT + \ 2154 AT91C_US_PAR_NONE + \ 2155 AT91C_US_CHRL_8_BITS + \ 2156 AT91C_US_CLKS_EXT ) 2157 2158 //* Standard Synchronous Mode : 8 bits , 1 stop , no parity 2159 #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ 2160 AT91C_US_USMODE_NORMAL + \ 2161 AT91C_US_NBSTOP_1_BIT + \ 2162 AT91C_US_PAR_NONE + \ 2163 AT91C_US_CHRL_8_BITS + \ 2164 AT91C_US_CLKS_CLOCK ) 2165 2166 //* SCK used Label 2167 #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) 2168 2169 //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity 2170 #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ 2171 AT91C_US_CLKS_CLOCK +\ 2172 AT91C_US_NBSTOP_1_BIT + \ 2173 AT91C_US_PAR_EVEN + \ 2174 AT91C_US_CHRL_8_BITS + \ 2175 AT91C_US_CKLO +\ 2176 AT91C_US_OVER) 2177 2178 //* Standard IRDA mode 2179 #define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ 2180 AT91C_US_NBSTOP_1_BIT + \ 2181 AT91C_US_PAR_NONE + \ 2182 AT91C_US_CHRL_8_BITS + \ 2183 AT91C_US_CLKS_CLOCK ) 2184 2185 //*---------------------------------------------------------------------------- 2186 //* \fn AT91F_US_Baudrate 2187 //* \brief Caluculate baud_value according to the main clock and the baud rate 2188 //*---------------------------------------------------------------------------- AT91F_US_Baudrate(const unsigned int main_clock,const unsigned int baud_rate)2189__inline unsigned int AT91F_US_Baudrate ( 2190 const unsigned int main_clock, // \arg peripheral clock 2191 const unsigned int baud_rate) // \arg UART baudrate 2192 { 2193 unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); 2194 if ((baud_value % 10) >= 5) 2195 baud_value = (baud_value / 10) + 1; 2196 else 2197 baud_value /= 10; 2198 return baud_value; 2199 } 2200 2201 //*---------------------------------------------------------------------------- 2202 //* \fn AT91F_US_SetBaudrate 2203 //* \brief Set the baudrate according to the CPU clock 2204 //*---------------------------------------------------------------------------- AT91F_US_SetBaudrate(AT91PS_USART pUSART,unsigned int mainClock,unsigned int speed)2205__inline void AT91F_US_SetBaudrate ( 2206 AT91PS_USART pUSART, // \arg pointer to a USART controller 2207 unsigned int mainClock, // \arg peripheral clock 2208 unsigned int speed) // \arg UART baudrate 2209 { 2210 //* Define the baud rate divisor register 2211 pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); 2212 } 2213 2214 //*---------------------------------------------------------------------------- 2215 //* \fn AT91F_US_SetTimeguard 2216 //* \brief Set USART timeguard 2217 //*---------------------------------------------------------------------------- AT91F_US_SetTimeguard(AT91PS_USART pUSART,unsigned int timeguard)2218__inline void AT91F_US_SetTimeguard ( 2219 AT91PS_USART pUSART, // \arg pointer to a USART controller 2220 unsigned int timeguard) // \arg timeguard value 2221 { 2222 //* Write the Timeguard Register 2223 pUSART->US_TTGR = timeguard ; 2224 } 2225 2226 //*---------------------------------------------------------------------------- 2227 //* \fn AT91F_US_EnableIt 2228 //* \brief Enable USART IT 2229 //*---------------------------------------------------------------------------- AT91F_US_EnableIt(AT91PS_USART pUSART,unsigned int flag)2230__inline void AT91F_US_EnableIt ( 2231 AT91PS_USART pUSART, // \arg pointer to a USART controller 2232 unsigned int flag) // \arg IT to be enabled 2233 { 2234 //* Write to the IER register 2235 pUSART->US_IER = flag; 2236 } 2237 2238 //*---------------------------------------------------------------------------- 2239 //* \fn AT91F_US_DisableIt 2240 //* \brief Disable USART IT 2241 //*---------------------------------------------------------------------------- AT91F_US_DisableIt(AT91PS_USART pUSART,unsigned int flag)2242__inline void AT91F_US_DisableIt ( 2243 AT91PS_USART pUSART, // \arg pointer to a USART controller 2244 unsigned int flag) // \arg IT to be disabled 2245 { 2246 //* Write to the IER register 2247 pUSART->US_IDR = flag; 2248 } 2249 2250 //*---------------------------------------------------------------------------- 2251 //* \fn AT91F_US_Configure 2252 //* \brief Configure USART 2253 //*---------------------------------------------------------------------------- AT91F_US_Configure(AT91PS_USART pUSART,unsigned int mainClock,unsigned int mode,unsigned int baudRate,unsigned int timeguard)2254__inline void AT91F_US_Configure ( 2255 AT91PS_USART pUSART, // \arg pointer to a USART controller 2256 unsigned int mainClock, // \arg peripheral clock 2257 unsigned int mode , // \arg mode Register to be programmed 2258 unsigned int baudRate , // \arg baudrate to be programmed 2259 unsigned int timeguard ) // \arg timeguard to be programmed 2260 { 2261 //* Disable interrupts 2262 pUSART->US_IDR = (unsigned int) -1; 2263 2264 //* Reset receiver and transmitter 2265 pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; 2266 2267 //* Define the baud rate divisor register 2268 AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); 2269 2270 //* Write the Timeguard Register 2271 AT91F_US_SetTimeguard(pUSART, timeguard); 2272 2273 //* Clear Transmit and Receive Counters 2274 AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); 2275 2276 //* Define the USART mode 2277 pUSART->US_MR = mode ; 2278 2279 } 2280 2281 //*---------------------------------------------------------------------------- 2282 //* \fn AT91F_US_EnableRx 2283 //* \brief Enable receiving characters 2284 //*---------------------------------------------------------------------------- AT91F_US_EnableRx(AT91PS_USART pUSART)2285__inline void AT91F_US_EnableRx ( 2286 AT91PS_USART pUSART) // \arg pointer to a USART controller 2287 { 2288 //* Enable receiver 2289 pUSART->US_CR = AT91C_US_RXEN; 2290 } 2291 2292 //*---------------------------------------------------------------------------- 2293 //* \fn AT91F_US_EnableTx 2294 //* \brief Enable sending characters 2295 //*---------------------------------------------------------------------------- AT91F_US_EnableTx(AT91PS_USART pUSART)2296__inline void AT91F_US_EnableTx ( 2297 AT91PS_USART pUSART) // \arg pointer to a USART controller 2298 { 2299 //* Enable transmitter 2300 pUSART->US_CR = AT91C_US_TXEN; 2301 } 2302 2303 //*---------------------------------------------------------------------------- 2304 //* \fn AT91F_US_ResetRx 2305 //* \brief Reset Receiver and re-enable it 2306 //*---------------------------------------------------------------------------- AT91F_US_ResetRx(AT91PS_USART pUSART)2307__inline void AT91F_US_ResetRx ( 2308 AT91PS_USART pUSART) // \arg pointer to a USART controller 2309 { 2310 //* Reset receiver 2311 pUSART->US_CR = AT91C_US_RSTRX; 2312 //* Re-Enable receiver 2313 pUSART->US_CR = AT91C_US_RXEN; 2314 } 2315 2316 //*---------------------------------------------------------------------------- 2317 //* \fn AT91F_US_ResetTx 2318 //* \brief Reset Transmitter and re-enable it 2319 //*---------------------------------------------------------------------------- AT91F_US_ResetTx(AT91PS_USART pUSART)2320__inline void AT91F_US_ResetTx ( 2321 AT91PS_USART pUSART) // \arg pointer to a USART controller 2322 { 2323 //* Reset transmitter 2324 pUSART->US_CR = AT91C_US_RSTTX; 2325 //* Enable transmitter 2326 pUSART->US_CR = AT91C_US_TXEN; 2327 } 2328 2329 //*---------------------------------------------------------------------------- 2330 //* \fn AT91F_US_DisableRx 2331 //* \brief Disable Receiver 2332 //*---------------------------------------------------------------------------- AT91F_US_DisableRx(AT91PS_USART pUSART)2333__inline void AT91F_US_DisableRx ( 2334 AT91PS_USART pUSART) // \arg pointer to a USART controller 2335 { 2336 //* Disable receiver 2337 pUSART->US_CR = AT91C_US_RXDIS; 2338 } 2339 2340 //*---------------------------------------------------------------------------- 2341 //* \fn AT91F_US_DisableTx 2342 //* \brief Disable Transmitter 2343 //*---------------------------------------------------------------------------- AT91F_US_DisableTx(AT91PS_USART pUSART)2344__inline void AT91F_US_DisableTx ( 2345 AT91PS_USART pUSART) // \arg pointer to a USART controller 2346 { 2347 //* Disable transmitter 2348 pUSART->US_CR = AT91C_US_TXDIS; 2349 } 2350 2351 //*---------------------------------------------------------------------------- 2352 //* \fn AT91F_US_Close 2353 //* \brief Close USART: disable IT disable receiver and transmitter, close PDC 2354 //*---------------------------------------------------------------------------- AT91F_US_Close(AT91PS_USART pUSART)2355__inline void AT91F_US_Close ( 2356 AT91PS_USART pUSART) // \arg pointer to a USART controller 2357 { 2358 //* Reset the baud rate divisor register 2359 pUSART->US_BRGR = 0 ; 2360 2361 //* Reset the USART mode 2362 pUSART->US_MR = 0 ; 2363 2364 //* Reset the Timeguard Register 2365 pUSART->US_TTGR = 0; 2366 2367 //* Disable all interrupts 2368 pUSART->US_IDR = 0xFFFFFFFF ; 2369 2370 //* Abort the Peripheral Data Transfers 2371 AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); 2372 2373 //* Disable receiver and transmitter and stop any activity immediately 2374 pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; 2375 } 2376 2377 //*---------------------------------------------------------------------------- 2378 //* \fn AT91F_US_TxReady 2379 //* \brief Return 1 if a character can be written in US_THR 2380 //*---------------------------------------------------------------------------- AT91F_US_TxReady(AT91PS_USART pUSART)2381__inline unsigned int AT91F_US_TxReady ( 2382 AT91PS_USART pUSART ) // \arg pointer to a USART controller 2383 { 2384 return (pUSART->US_CSR & AT91C_US_TXRDY); 2385 } 2386 2387 //*---------------------------------------------------------------------------- 2388 //* \fn AT91F_US_RxReady 2389 //* \brief Return 1 if a character can be read in US_RHR 2390 //*---------------------------------------------------------------------------- AT91F_US_RxReady(AT91PS_USART pUSART)2391__inline unsigned int AT91F_US_RxReady ( 2392 AT91PS_USART pUSART ) // \arg pointer to a USART controller 2393 { 2394 return (pUSART->US_CSR & AT91C_US_RXRDY); 2395 } 2396 2397 //*---------------------------------------------------------------------------- 2398 //* \fn AT91F_US_Error 2399 //* \brief Return the error flag 2400 //*---------------------------------------------------------------------------- AT91F_US_Error(AT91PS_USART pUSART)2401__inline unsigned int AT91F_US_Error ( 2402 AT91PS_USART pUSART ) // \arg pointer to a USART controller 2403 { 2404 return (pUSART->US_CSR & 2405 (AT91C_US_OVRE | // Overrun error 2406 AT91C_US_FRAME | // Framing error 2407 AT91C_US_PARE)); // Parity error 2408 } 2409 2410 //*---------------------------------------------------------------------------- 2411 //* \fn AT91F_US_PutChar 2412 //* \brief Send a character,does not check if ready to send 2413 //*---------------------------------------------------------------------------- AT91F_US_PutChar(AT91PS_USART pUSART,int character)2414__inline void AT91F_US_PutChar ( 2415 AT91PS_USART pUSART, 2416 int character ) 2417 { 2418 pUSART->US_THR = (character & 0x1FF); 2419 } 2420 2421 //*---------------------------------------------------------------------------- 2422 //* \fn AT91F_US_GetChar 2423 //* \brief Receive a character,does not check if a character is available 2424 //*---------------------------------------------------------------------------- AT91F_US_GetChar(const AT91PS_USART pUSART)2425__inline int AT91F_US_GetChar ( 2426 const AT91PS_USART pUSART) 2427 { 2428 return((pUSART->US_RHR) & 0x1FF); 2429 } 2430 2431 //*---------------------------------------------------------------------------- 2432 //* \fn AT91F_US_SendFrame 2433 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy 2434 //*---------------------------------------------------------------------------- AT91F_US_SendFrame(AT91PS_USART pUSART,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)2435__inline unsigned int AT91F_US_SendFrame( 2436 AT91PS_USART pUSART, 2437 char *pBuffer, 2438 unsigned int szBuffer, 2439 char *pNextBuffer, 2440 unsigned int szNextBuffer ) 2441 { 2442 return AT91F_PDC_SendFrame( 2443 (AT91PS_PDC) &(pUSART->US_RPR), 2444 pBuffer, 2445 szBuffer, 2446 pNextBuffer, 2447 szNextBuffer); 2448 } 2449 2450 //*---------------------------------------------------------------------------- 2451 //* \fn AT91F_US_ReceiveFrame 2452 //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy 2453 //*---------------------------------------------------------------------------- AT91F_US_ReceiveFrame(AT91PS_USART pUSART,char * pBuffer,unsigned int szBuffer,char * pNextBuffer,unsigned int szNextBuffer)2454__inline unsigned int AT91F_US_ReceiveFrame ( 2455 AT91PS_USART pUSART, 2456 char *pBuffer, 2457 unsigned int szBuffer, 2458 char *pNextBuffer, 2459 unsigned int szNextBuffer ) 2460 { 2461 return AT91F_PDC_ReceiveFrame( 2462 (AT91PS_PDC) &(pUSART->US_RPR), 2463 pBuffer, 2464 szBuffer, 2465 pNextBuffer, 2466 szNextBuffer); 2467 } 2468 2469 //*---------------------------------------------------------------------------- 2470 //* \fn AT91F_US_SetIrdaFilter 2471 //* \brief Set the value of IrDa filter tregister 2472 //*---------------------------------------------------------------------------- AT91F_US_SetIrdaFilter(AT91PS_USART pUSART,unsigned char value)2473__inline void AT91F_US_SetIrdaFilter ( 2474 AT91PS_USART pUSART, 2475 unsigned char value 2476 ) 2477 { 2478 pUSART->US_IF = value; 2479 } 2480 2481 /* ***************************************************************************** 2482 SOFTWARE API FOR UDP 2483 ***************************************************************************** */ 2484 //*---------------------------------------------------------------------------- 2485 //* \fn AT91F_UDP_EnableIt 2486 //* \brief Enable UDP IT 2487 //*---------------------------------------------------------------------------- AT91F_UDP_EnableIt(AT91PS_UDP pUDP,unsigned int flag)2488__inline void AT91F_UDP_EnableIt ( 2489 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2490 unsigned int flag) // \arg IT to be enabled 2491 { 2492 //* Write to the IER register 2493 pUDP->UDP_IER = flag; 2494 } 2495 2496 //*---------------------------------------------------------------------------- 2497 //* \fn AT91F_UDP_DisableIt 2498 //* \brief Disable UDP IT 2499 //*---------------------------------------------------------------------------- AT91F_UDP_DisableIt(AT91PS_UDP pUDP,unsigned int flag)2500__inline void AT91F_UDP_DisableIt ( 2501 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2502 unsigned int flag) // \arg IT to be disabled 2503 { 2504 //* Write to the IDR register 2505 pUDP->UDP_IDR = flag; 2506 } 2507 2508 //*---------------------------------------------------------------------------- 2509 //* \fn AT91F_UDP_SetAddress 2510 //* \brief Set UDP functional address 2511 //*---------------------------------------------------------------------------- AT91F_UDP_SetAddress(AT91PS_UDP pUDP,unsigned char address)2512__inline void AT91F_UDP_SetAddress ( 2513 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2514 unsigned char address) // \arg new UDP address 2515 { 2516 pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); 2517 } 2518 2519 //*---------------------------------------------------------------------------- 2520 //* \fn AT91F_UDP_EnableEp 2521 //* \brief Enable Endpoint 2522 //*---------------------------------------------------------------------------- AT91F_UDP_EnableEp(AT91PS_UDP pUDP,unsigned int flag)2523__inline void AT91F_UDP_EnableEp ( 2524 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2525 unsigned int flag) // \arg endpoints to be enabled 2526 { 2527 pUDP->UDP_GLBSTATE |= flag; 2528 } 2529 2530 //*---------------------------------------------------------------------------- 2531 //* \fn AT91F_UDP_DisableEp 2532 //* \brief Enable Endpoint 2533 //*---------------------------------------------------------------------------- AT91F_UDP_DisableEp(AT91PS_UDP pUDP,unsigned int flag)2534__inline void AT91F_UDP_DisableEp ( 2535 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2536 unsigned int flag) // \arg endpoints to be enabled 2537 { 2538 pUDP->UDP_GLBSTATE &= ~(flag); 2539 } 2540 2541 //*---------------------------------------------------------------------------- 2542 //* \fn AT91F_UDP_SetState 2543 //* \brief Set UDP Device state 2544 //*---------------------------------------------------------------------------- AT91F_UDP_SetState(AT91PS_UDP pUDP,unsigned int flag)2545__inline void AT91F_UDP_SetState ( 2546 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2547 unsigned int flag) // \arg new UDP address 2548 { 2549 pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); 2550 pUDP->UDP_GLBSTATE |= flag; 2551 } 2552 2553 //*---------------------------------------------------------------------------- 2554 //* \fn AT91F_UDP_GetState 2555 //* \brief return UDP Device state 2556 //*---------------------------------------------------------------------------- AT91F_UDP_GetState(AT91PS_UDP pUDP)2557__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state 2558 AT91PS_UDP pUDP) // \arg pointer to a UDP controller 2559 { 2560 return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); 2561 } 2562 2563 //*---------------------------------------------------------------------------- 2564 //* \fn AT91F_UDP_ResetEp 2565 //* \brief Reset UDP endpoint 2566 //*---------------------------------------------------------------------------- AT91F_UDP_ResetEp(AT91PS_UDP pUDP,unsigned int flag)2567__inline void AT91F_UDP_ResetEp ( // \return the UDP device state 2568 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2569 unsigned int flag) // \arg Endpoints to be reset 2570 { 2571 pUDP->UDP_RSTEP = flag; 2572 } 2573 2574 //*---------------------------------------------------------------------------- 2575 //* \fn AT91F_UDP_EpStall 2576 //* \brief Endpoint will STALL requests 2577 //*---------------------------------------------------------------------------- AT91F_UDP_EpStall(AT91PS_UDP pUDP,unsigned char endpoint)2578__inline void AT91F_UDP_EpStall( 2579 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2580 unsigned char endpoint) // \arg endpoint number 2581 { 2582 pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; 2583 } 2584 2585 //*---------------------------------------------------------------------------- 2586 //* \fn AT91F_UDP_EpWrite 2587 //* \brief Write value in the DPR 2588 //*---------------------------------------------------------------------------- AT91F_UDP_EpWrite(AT91PS_UDP pUDP,unsigned char endpoint,unsigned char value)2589__inline void AT91F_UDP_EpWrite( 2590 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2591 unsigned char endpoint, // \arg endpoint number 2592 unsigned char value) // \arg value to be written in the DPR 2593 { 2594 pUDP->UDP_FDR[endpoint] = value; 2595 } 2596 2597 //*---------------------------------------------------------------------------- 2598 //* \fn AT91F_UDP_EpRead 2599 //* \brief Return value from the DPR 2600 //*---------------------------------------------------------------------------- AT91F_UDP_EpRead(AT91PS_UDP pUDP,unsigned char endpoint)2601__inline unsigned int AT91F_UDP_EpRead( 2602 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2603 unsigned char endpoint) // \arg endpoint number 2604 { 2605 return pUDP->UDP_FDR[endpoint]; 2606 } 2607 2608 //*---------------------------------------------------------------------------- 2609 //* \fn AT91F_UDP_EpEndOfWr 2610 //* \brief Notify the UDP that values in DPR are ready to be sent 2611 //*---------------------------------------------------------------------------- AT91F_UDP_EpEndOfWr(AT91PS_UDP pUDP,unsigned char endpoint)2612__inline void AT91F_UDP_EpEndOfWr( 2613 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2614 unsigned char endpoint) // \arg endpoint number 2615 { 2616 pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; 2617 } 2618 2619 //*---------------------------------------------------------------------------- 2620 //* \fn AT91F_UDP_EpClear 2621 //* \brief Clear flag in the endpoint CSR register 2622 //*---------------------------------------------------------------------------- AT91F_UDP_EpClear(AT91PS_UDP pUDP,unsigned char endpoint,unsigned int flag)2623__inline void AT91F_UDP_EpClear( 2624 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2625 unsigned char endpoint, // \arg endpoint number 2626 unsigned int flag) // \arg flag to be cleared 2627 { 2628 pUDP->UDP_CSR[endpoint] &= ~(flag); 2629 } 2630 2631 //*---------------------------------------------------------------------------- 2632 //* \fn AT91F_UDP_EpSet 2633 //* \brief Set flag in the endpoint CSR register 2634 //*---------------------------------------------------------------------------- AT91F_UDP_EpSet(AT91PS_UDP pUDP,unsigned char endpoint,unsigned int flag)2635__inline void AT91F_UDP_EpSet( 2636 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2637 unsigned char endpoint, // \arg endpoint number 2638 unsigned int flag) // \arg flag to be cleared 2639 { 2640 pUDP->UDP_CSR[endpoint] |= flag; 2641 } 2642 2643 //*---------------------------------------------------------------------------- 2644 //* \fn AT91F_UDP_EpStatus 2645 //* \brief Return the endpoint CSR register 2646 //*---------------------------------------------------------------------------- AT91F_UDP_EpStatus(AT91PS_UDP pUDP,unsigned char endpoint)2647__inline unsigned int AT91F_UDP_EpStatus( 2648 AT91PS_UDP pUDP, // \arg pointer to a UDP controller 2649 unsigned char endpoint) // \arg endpoint number 2650 { 2651 return pUDP->UDP_CSR[endpoint]; 2652 } 2653 2654 //*---------------------------------------------------------------------------- 2655 //* \fn AT91F_UDP_GetInterruptMaskStatus 2656 //* \brief Return UDP Interrupt Mask Status 2657 //*---------------------------------------------------------------------------- AT91F_UDP_GetInterruptMaskStatus(AT91PS_UDP pUdp)2658__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status 2659 AT91PS_UDP pUdp) // \arg pointer to a UDP controller 2660 { 2661 return pUdp->UDP_IMR; 2662 } 2663 2664 //*---------------------------------------------------------------------------- 2665 //* \fn AT91F_UDP_IsInterruptMasked 2666 //* \brief Test if UDP Interrupt is Masked 2667 //*---------------------------------------------------------------------------- AT91F_UDP_IsInterruptMasked(AT91PS_UDP pUdp,unsigned int flag)2668__inline int AT91F_UDP_IsInterruptMasked( 2669 AT91PS_UDP pUdp, // \arg pointer to a UDP controller 2670 unsigned int flag) // \arg flag to be tested 2671 { 2672 return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); 2673 } 2674 2675 /* ***************************************************************************** 2676 SOFTWARE API FOR AIC 2677 ***************************************************************************** */ 2678 #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] 2679 2680 //*---------------------------------------------------------------------------- 2681 //* \fn AT91F_AIC_ConfigureIt 2682 //* \brief Interrupt Handler Initialization 2683 //*---------------------------------------------------------------------------- AT91F_AIC_ConfigureIt(AT91PS_AIC pAic,unsigned int irq_id,unsigned int priority,unsigned int src_type,void (* newHandler)(void))2684__inline unsigned int AT91F_AIC_ConfigureIt ( 2685 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2686 unsigned int irq_id, // \arg interrupt number to initialize 2687 unsigned int priority, // \arg priority to give to the interrupt 2688 unsigned int src_type, // \arg activation and sense of activation 2689 void (*newHandler) (void) ) // \arg address of the interrupt handler 2690 { 2691 unsigned int oldHandler; 2692 unsigned int mask ; 2693 2694 oldHandler = pAic->AIC_SVR[irq_id]; 2695 2696 mask = 0x1 << irq_id ; 2697 //* Disable the interrupt on the interrupt controller 2698 pAic->AIC_IDCR = mask ; 2699 //* Save the interrupt handler routine pointer and the interrupt priority 2700 pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; 2701 //* Store the Source Mode Register 2702 pAic->AIC_SMR[irq_id] = src_type | priority ; 2703 //* Clear the interrupt on the interrupt controller 2704 pAic->AIC_ICCR = mask ; 2705 2706 return oldHandler; 2707 } 2708 2709 //*---------------------------------------------------------------------------- 2710 //* \fn AT91F_AIC_EnableIt 2711 //* \brief Enable corresponding IT number 2712 //*---------------------------------------------------------------------------- AT91F_AIC_EnableIt(AT91PS_AIC pAic,unsigned int irq_id)2713__inline void AT91F_AIC_EnableIt ( 2714 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2715 unsigned int irq_id ) // \arg interrupt number to initialize 2716 { 2717 //* Enable the interrupt on the interrupt controller 2718 pAic->AIC_IECR = 0x1 << irq_id ; 2719 } 2720 2721 //*---------------------------------------------------------------------------- 2722 //* \fn AT91F_AIC_DisableIt 2723 //* \brief Disable corresponding IT number 2724 //*---------------------------------------------------------------------------- AT91F_AIC_DisableIt(AT91PS_AIC pAic,unsigned int irq_id)2725__inline void AT91F_AIC_DisableIt ( 2726 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2727 unsigned int irq_id ) // \arg interrupt number to initialize 2728 { 2729 unsigned int mask = 0x1 << irq_id; 2730 //* Disable the interrupt on the interrupt controller 2731 pAic->AIC_IDCR = mask ; 2732 //* Clear the interrupt on the Interrupt Controller ( if one is pending ) 2733 pAic->AIC_ICCR = mask ; 2734 } 2735 2736 //*---------------------------------------------------------------------------- 2737 //* \fn AT91F_AIC_ClearIt 2738 //* \brief Clear corresponding IT number 2739 //*---------------------------------------------------------------------------- AT91F_AIC_ClearIt(AT91PS_AIC pAic,unsigned int irq_id)2740__inline void AT91F_AIC_ClearIt ( 2741 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2742 unsigned int irq_id) // \arg interrupt number to initialize 2743 { 2744 //* Clear the interrupt on the Interrupt Controller ( if one is pending ) 2745 pAic->AIC_ICCR = (0x1 << irq_id); 2746 } 2747 2748 //*---------------------------------------------------------------------------- 2749 //* \fn AT91F_AIC_AcknowledgeIt 2750 //* \brief Acknowledge corresponding IT number 2751 //*---------------------------------------------------------------------------- AT91F_AIC_AcknowledgeIt(AT91PS_AIC pAic)2752__inline void AT91F_AIC_AcknowledgeIt ( 2753 AT91PS_AIC pAic) // \arg pointer to the AIC registers 2754 { 2755 pAic->AIC_EOICR = pAic->AIC_EOICR; 2756 } 2757 2758 //*---------------------------------------------------------------------------- 2759 //* \fn AT91F_AIC_SetExceptionVector 2760 //* \brief Configure vector handler 2761 //*---------------------------------------------------------------------------- AT91F_AIC_SetExceptionVector(unsigned int * pVector,void (* Handler)())2762__inline unsigned int AT91F_AIC_SetExceptionVector ( 2763 unsigned int *pVector, // \arg pointer to the AIC registers 2764 void (*Handler) () ) // \arg Interrupt Handler 2765 { 2766 unsigned int oldVector = *pVector; 2767 2768 if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) 2769 *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; 2770 else 2771 *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; 2772 2773 return oldVector; 2774 } 2775 2776 //*---------------------------------------------------------------------------- 2777 //* \fn AT91F_AIC_Trig 2778 //* \brief Trig an IT 2779 //*---------------------------------------------------------------------------- AT91F_AIC_Trig(AT91PS_AIC pAic,unsigned int irq_id)2780__inline void AT91F_AIC_Trig ( 2781 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2782 unsigned int irq_id) // \arg interrupt number 2783 { 2784 pAic->AIC_ISCR = (0x1 << irq_id) ; 2785 } 2786 2787 //*---------------------------------------------------------------------------- 2788 //* \fn AT91F_AIC_IsActive 2789 //* \brief Test if an IT is active 2790 //*---------------------------------------------------------------------------- AT91F_AIC_IsActive(AT91PS_AIC pAic,unsigned int irq_id)2791__inline unsigned int AT91F_AIC_IsActive ( 2792 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2793 unsigned int irq_id) // \arg Interrupt Number 2794 { 2795 return (pAic->AIC_ISR & (0x1 << irq_id)); 2796 } 2797 2798 //*---------------------------------------------------------------------------- 2799 //* \fn AT91F_AIC_IsPending 2800 //* \brief Test if an IT is pending 2801 //*---------------------------------------------------------------------------- AT91F_AIC_IsPending(AT91PS_AIC pAic,unsigned int irq_id)2802__inline unsigned int AT91F_AIC_IsPending ( 2803 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2804 unsigned int irq_id) // \arg Interrupt Number 2805 { 2806 return (pAic->AIC_IPR & (0x1 << irq_id)); 2807 } 2808 2809 //*---------------------------------------------------------------------------- 2810 //* \fn AT91F_AIC_Open 2811 //* \brief Set exception vectors and AIC registers to default values 2812 //*---------------------------------------------------------------------------- AT91F_AIC_Open(AT91PS_AIC pAic,void (* IrqHandler)(),void (* FiqHandler)(),void (* DefaultHandler)(),void (* SpuriousHandler)(),unsigned int protectMode)2813__inline void AT91F_AIC_Open( 2814 AT91PS_AIC pAic, // \arg pointer to the AIC registers 2815 void (*IrqHandler) (), // \arg Default IRQ vector exception 2816 void (*FiqHandler) (), // \arg Default FIQ vector exception 2817 void (*DefaultHandler) (), // \arg Default Handler set in ISR 2818 void (*SpuriousHandler) (), // \arg Default Spurious Handler 2819 unsigned int protectMode) // \arg Debug Control Register 2820 { 2821 int i; 2822 2823 // Disable all interrupts and set IVR to the default handler 2824 for (i = 0; i < 32; ++i) { 2825 AT91F_AIC_DisableIt(pAic, i); 2826 AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); 2827 } 2828 2829 // Set the IRQ exception vector 2830 AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); 2831 // Set the Fast Interrupt exception vector 2832 AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); 2833 2834 pAic->AIC_SPU = (unsigned int) SpuriousHandler; 2835 pAic->AIC_DCR = protectMode; 2836 } 2837 //*---------------------------------------------------------------------------- 2838 //* \fn AT91F_MC_CfgPMC 2839 //* \brief Enable Peripheral clock in PMC for MC 2840 //*---------------------------------------------------------------------------- AT91F_MC_CfgPMC(void)2841__inline void AT91F_MC_CfgPMC (void) 2842 { 2843 AT91F_PMC_EnablePeriphClock( 2844 AT91C_BASE_PMC, // PIO controller base address 2845 ((unsigned int) 1 << AT91C_ID_SYS)); 2846 } 2847 2848 //*---------------------------------------------------------------------------- 2849 //* \fn AT91F_DBGU_CfgPMC 2850 //* \brief Enable Peripheral clock in PMC for DBGU 2851 //*---------------------------------------------------------------------------- AT91F_DBGU_CfgPMC(void)2852__inline void AT91F_DBGU_CfgPMC (void) 2853 { 2854 AT91F_PMC_EnablePeriphClock( 2855 AT91C_BASE_PMC, // PIO controller base address 2856 ((unsigned int) 1 << AT91C_ID_SYS)); 2857 } 2858 2859 //*---------------------------------------------------------------------------- 2860 //* \fn AT91F_DBGU_CfgPIO 2861 //* \brief Configure PIO controllers to drive DBGU signals 2862 //*---------------------------------------------------------------------------- AT91F_DBGU_CfgPIO(void)2863__inline void AT91F_DBGU_CfgPIO (void) 2864 { 2865 // Configure PIO controllers to periph mode 2866 AT91F_PIO_CfgPeriph( 2867 AT91C_BASE_PIOA, // PIO controller base address 2868 ((unsigned int) AT91C_PA10_DTXD ) | 2869 ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A 2870 0); // Peripheral B 2871 } 2872 2873 //*---------------------------------------------------------------------------- 2874 //* \fn AT91F_PWMC_CH3_CfgPIO 2875 //* \brief Configure PIO controllers to drive PWMC_CH3 signals 2876 //*---------------------------------------------------------------------------- AT91F_PWMC_CH3_CfgPIO(void)2877__inline void AT91F_PWMC_CH3_CfgPIO (void) 2878 { 2879 // Configure PIO controllers to periph mode 2880 AT91F_PIO_CfgPeriph( 2881 AT91C_BASE_PIOA, // PIO controller base address 2882 0, // Peripheral A 2883 ((unsigned int) AT91C_PA14_PWM3 ) | 2884 ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B 2885 } 2886 2887 //*---------------------------------------------------------------------------- 2888 //* \fn AT91F_PWMC_CH2_CfgPIO 2889 //* \brief Configure PIO controllers to drive PWMC_CH2 signals 2890 //*---------------------------------------------------------------------------- AT91F_PWMC_CH2_CfgPIO(void)2891__inline void AT91F_PWMC_CH2_CfgPIO (void) 2892 { 2893 // Configure PIO controllers to periph mode 2894 AT91F_PIO_CfgPeriph( 2895 AT91C_BASE_PIOA, // PIO controller base address 2896 ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A 2897 ((unsigned int) AT91C_PA25_PWM2 ) | 2898 ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B 2899 } 2900 2901 //*---------------------------------------------------------------------------- 2902 //* \fn AT91F_PWMC_CH1_CfgPIO 2903 //* \brief Configure PIO controllers to drive PWMC_CH1 signals 2904 //*---------------------------------------------------------------------------- AT91F_PWMC_CH1_CfgPIO(void)2905__inline void AT91F_PWMC_CH1_CfgPIO (void) 2906 { 2907 // Configure PIO controllers to periph mode 2908 AT91F_PIO_CfgPeriph( 2909 AT91C_BASE_PIOA, // PIO controller base address 2910 ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A 2911 ((unsigned int) AT91C_PA24_PWM1 ) | 2912 ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B 2913 } 2914 2915 //*---------------------------------------------------------------------------- 2916 //* \fn AT91F_PWMC_CH0_CfgPIO 2917 //* \brief Configure PIO controllers to drive PWMC_CH0 signals 2918 //*---------------------------------------------------------------------------- AT91F_PWMC_CH0_CfgPIO(void)2919__inline void AT91F_PWMC_CH0_CfgPIO (void) 2920 { 2921 // Configure PIO controllers to periph mode 2922 AT91F_PIO_CfgPeriph( 2923 AT91C_BASE_PIOA, // PIO controller base address 2924 ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A 2925 ((unsigned int) AT91C_PA23_PWM0 ) | 2926 ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B 2927 } 2928 2929 //*---------------------------------------------------------------------------- 2930 //* \fn AT91F_SSC_CfgPMC 2931 //* \brief Enable Peripheral clock in PMC for SSC 2932 //*---------------------------------------------------------------------------- AT91F_SSC_CfgPMC(void)2933__inline void AT91F_SSC_CfgPMC (void) 2934 { 2935 AT91F_PMC_EnablePeriphClock( 2936 AT91C_BASE_PMC, // PIO controller base address 2937 ((unsigned int) 1 << AT91C_ID_SSC)); 2938 } 2939 2940 //*---------------------------------------------------------------------------- 2941 //* \fn AT91F_SSC_CfgPIO 2942 //* \brief Configure PIO controllers to drive SSC signals 2943 //*---------------------------------------------------------------------------- AT91F_SSC_CfgPIO(void)2944__inline void AT91F_SSC_CfgPIO (void) 2945 { 2946 // Configure PIO controllers to periph mode 2947 AT91F_PIO_CfgPeriph( 2948 AT91C_BASE_PIOA, // PIO controller base address 2949 ((unsigned int) AT91C_PA17_TD ) | 2950 ((unsigned int) AT91C_PA15_TF ) | 2951 ((unsigned int) AT91C_PA19_RK ) | 2952 ((unsigned int) AT91C_PA18_RD ) | 2953 ((unsigned int) AT91C_PA20_RF ) | 2954 ((unsigned int) AT91C_PA16_TK ), // Peripheral A 2955 0); // Peripheral B 2956 } 2957 2958 //*---------------------------------------------------------------------------- 2959 //* \fn AT91F_SPI_CfgPMC 2960 //* \brief Enable Peripheral clock in PMC for SPI 2961 //*---------------------------------------------------------------------------- AT91F_SPI_CfgPMC(void)2962__inline void AT91F_SPI_CfgPMC (void) 2963 { 2964 AT91F_PMC_EnablePeriphClock( 2965 AT91C_BASE_PMC, // PIO controller base address 2966 ((unsigned int) 1 << AT91C_ID_SPI)); 2967 } 2968 2969 //*---------------------------------------------------------------------------- 2970 //* \fn AT91F_SPI_CfgPIO 2971 //* \brief Configure PIO controllers to drive SPI signals 2972 //*---------------------------------------------------------------------------- AT91F_SPI_CfgPIO(void)2973__inline void AT91F_SPI_CfgPIO (void) 2974 { 2975 // Configure PIO controllers to periph mode 2976 AT91F_PIO_CfgPeriph( 2977 AT91C_BASE_PIOA, // PIO controller base address 2978 ((unsigned int) AT91C_PA11_NPCS0 ) | 2979 ((unsigned int) AT91C_PA13_MOSI ) | 2980 ((unsigned int) AT91C_PA31_NPCS1 ) | 2981 ((unsigned int) AT91C_PA12_MISO ) | 2982 ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A 2983 ((unsigned int) AT91C_PA9_NPCS1 ) | 2984 ((unsigned int) AT91C_PA30_NPCS2 ) | 2985 ((unsigned int) AT91C_PA10_NPCS2 ) | 2986 ((unsigned int) AT91C_PA22_NPCS3 ) | 2987 ((unsigned int) AT91C_PA3_NPCS3 ) | 2988 ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B 2989 } 2990 2991 //*---------------------------------------------------------------------------- 2992 //* \fn AT91F_PWMC_CfgPMC 2993 //* \brief Enable Peripheral clock in PMC for PWMC 2994 //*---------------------------------------------------------------------------- AT91F_PWMC_CfgPMC(void)2995__inline void AT91F_PWMC_CfgPMC (void) 2996 { 2997 AT91F_PMC_EnablePeriphClock( 2998 AT91C_BASE_PMC, // PIO controller base address 2999 ((unsigned int) 1 << AT91C_ID_PWMC)); 3000 } 3001 3002 //*---------------------------------------------------------------------------- 3003 //* \fn AT91F_TC2_CfgPMC 3004 //* \brief Enable Peripheral clock in PMC for TC2 3005 //*---------------------------------------------------------------------------- AT91F_TC2_CfgPMC(void)3006__inline void AT91F_TC2_CfgPMC (void) 3007 { 3008 AT91F_PMC_EnablePeriphClock( 3009 AT91C_BASE_PMC, // PIO controller base address 3010 ((unsigned int) 1 << AT91C_ID_TC2)); 3011 } 3012 3013 //*---------------------------------------------------------------------------- 3014 //* \fn AT91F_TC2_CfgPIO 3015 //* \brief Configure PIO controllers to drive TC2 signals 3016 //*---------------------------------------------------------------------------- AT91F_TC2_CfgPIO(void)3017__inline void AT91F_TC2_CfgPIO (void) 3018 { 3019 // Configure PIO controllers to periph mode 3020 AT91F_PIO_CfgPeriph( 3021 AT91C_BASE_PIOA, // PIO controller base address 3022 0, // Peripheral A 3023 ((unsigned int) AT91C_PA26_TIOA2 ) | 3024 ((unsigned int) AT91C_PA27_TIOB2 ) | 3025 ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B 3026 } 3027 3028 //*---------------------------------------------------------------------------- 3029 //* \fn AT91F_TC1_CfgPMC 3030 //* \brief Enable Peripheral clock in PMC for TC1 3031 //*---------------------------------------------------------------------------- AT91F_TC1_CfgPMC(void)3032__inline void AT91F_TC1_CfgPMC (void) 3033 { 3034 AT91F_PMC_EnablePeriphClock( 3035 AT91C_BASE_PMC, // PIO controller base address 3036 ((unsigned int) 1 << AT91C_ID_TC1)); 3037 } 3038 3039 //*---------------------------------------------------------------------------- 3040 //* \fn AT91F_TC1_CfgPIO 3041 //* \brief Configure PIO controllers to drive TC1 signals 3042 //*---------------------------------------------------------------------------- AT91F_TC1_CfgPIO(void)3043__inline void AT91F_TC1_CfgPIO (void) 3044 { 3045 // Configure PIO controllers to periph mode 3046 AT91F_PIO_CfgPeriph( 3047 AT91C_BASE_PIOA, // PIO controller base address 3048 0, // Peripheral A 3049 ((unsigned int) AT91C_PA15_TIOA1 ) | 3050 ((unsigned int) AT91C_PA16_TIOB1 ) | 3051 ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B 3052 } 3053 3054 //*---------------------------------------------------------------------------- 3055 //* \fn AT91F_TC0_CfgPMC 3056 //* \brief Enable Peripheral clock in PMC for TC0 3057 //*---------------------------------------------------------------------------- AT91F_TC0_CfgPMC(void)3058__inline void AT91F_TC0_CfgPMC (void) 3059 { 3060 AT91F_PMC_EnablePeriphClock( 3061 AT91C_BASE_PMC, // PIO controller base address 3062 ((unsigned int) 1 << AT91C_ID_TC0)); 3063 } 3064 3065 //*---------------------------------------------------------------------------- 3066 //* \fn AT91F_TC0_CfgPIO 3067 //* \brief Configure PIO controllers to drive TC0 signals 3068 //*---------------------------------------------------------------------------- AT91F_TC0_CfgPIO(void)3069__inline void AT91F_TC0_CfgPIO (void) 3070 { 3071 // Configure PIO controllers to periph mode 3072 AT91F_PIO_CfgPeriph( 3073 AT91C_BASE_PIOA, // PIO controller base address 3074 0, // Peripheral A 3075 ((unsigned int) AT91C_PA0_TIOA0 ) | 3076 ((unsigned int) AT91C_PA1_TIOB0 ) | 3077 ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B 3078 } 3079 3080 //*---------------------------------------------------------------------------- 3081 //* \fn AT91F_PMC_CfgPMC 3082 //* \brief Enable Peripheral clock in PMC for PMC 3083 //*---------------------------------------------------------------------------- AT91F_PMC_CfgPMC(void)3084__inline void AT91F_PMC_CfgPMC (void) 3085 { 3086 AT91F_PMC_EnablePeriphClock( 3087 AT91C_BASE_PMC, // PIO controller base address 3088 ((unsigned int) 1 << AT91C_ID_SYS)); 3089 } 3090 3091 //*---------------------------------------------------------------------------- 3092 //* \fn AT91F_PMC_CfgPIO 3093 //* \brief Configure PIO controllers to drive PMC signals 3094 //*---------------------------------------------------------------------------- AT91F_PMC_CfgPIO(void)3095__inline void AT91F_PMC_CfgPIO (void) 3096 { 3097 // Configure PIO controllers to periph mode 3098 AT91F_PIO_CfgPeriph( 3099 AT91C_BASE_PIOA, // PIO controller base address 3100 0, // Peripheral A 3101 ((unsigned int) AT91C_PA17_PCK1 ) | 3102 ((unsigned int) AT91C_PA21_PCK1 ) | 3103 ((unsigned int) AT91C_PA31_PCK2 ) | 3104 ((unsigned int) AT91C_PA18_PCK2 ) | 3105 ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B 3106 } 3107 3108 //*---------------------------------------------------------------------------- 3109 //* \fn AT91F_ADC_CfgPMC 3110 //* \brief Enable Peripheral clock in PMC for ADC 3111 //*---------------------------------------------------------------------------- AT91F_ADC_CfgPMC(void)3112__inline void AT91F_ADC_CfgPMC (void) 3113 { 3114 AT91F_PMC_EnablePeriphClock( 3115 AT91C_BASE_PMC, // PIO controller base address 3116 ((unsigned int) 1 << AT91C_ID_ADC)); 3117 } 3118 3119 //*---------------------------------------------------------------------------- 3120 //* \fn AT91F_ADC_CfgPIO 3121 //* \brief Configure PIO controllers to drive ADC signals 3122 //*---------------------------------------------------------------------------- AT91F_ADC_CfgPIO(void)3123__inline void AT91F_ADC_CfgPIO (void) 3124 { 3125 // Configure PIO controllers to periph mode 3126 AT91F_PIO_CfgPeriph( 3127 AT91C_BASE_PIOA, // PIO controller base address 3128 0, // Peripheral A 3129 ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B 3130 } 3131 3132 //*---------------------------------------------------------------------------- 3133 //* \fn AT91F_PIOA_CfgPMC 3134 //* \brief Enable Peripheral clock in PMC for PIOA 3135 //*---------------------------------------------------------------------------- AT91F_PIOA_CfgPMC(void)3136__inline void AT91F_PIOA_CfgPMC (void) 3137 { 3138 AT91F_PMC_EnablePeriphClock( 3139 AT91C_BASE_PMC, // PIO controller base address 3140 ((unsigned int) 1 << AT91C_ID_PIOA)); 3141 } 3142 3143 //*---------------------------------------------------------------------------- 3144 //* \fn AT91F_TWI_CfgPMC 3145 //* \brief Enable Peripheral clock in PMC for TWI 3146 //*---------------------------------------------------------------------------- AT91F_TWI_CfgPMC(void)3147__inline void AT91F_TWI_CfgPMC (void) 3148 { 3149 AT91F_PMC_EnablePeriphClock( 3150 AT91C_BASE_PMC, // PIO controller base address 3151 ((unsigned int) 1 << AT91C_ID_TWI)); 3152 } 3153 3154 //*---------------------------------------------------------------------------- 3155 //* \fn AT91F_TWI_CfgPIO 3156 //* \brief Configure PIO controllers to drive TWI signals 3157 //*---------------------------------------------------------------------------- AT91F_TWI_CfgPIO(void)3158__inline void AT91F_TWI_CfgPIO (void) 3159 { 3160 // Configure PIO controllers to periph mode 3161 AT91F_PIO_CfgPeriph( 3162 AT91C_BASE_PIOA, // PIO controller base address 3163 ((unsigned int) AT91C_PA3_TWD ) | 3164 ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A 3165 0); // Peripheral B 3166 } 3167 3168 //*---------------------------------------------------------------------------- 3169 //* \fn AT91F_US1_CfgPMC 3170 //* \brief Enable Peripheral clock in PMC for US1 3171 //*---------------------------------------------------------------------------- AT91F_US1_CfgPMC(void)3172__inline void AT91F_US1_CfgPMC (void) 3173 { 3174 AT91F_PMC_EnablePeriphClock( 3175 AT91C_BASE_PMC, // PIO controller base address 3176 ((unsigned int) 1 << AT91C_ID_US1)); 3177 } 3178 3179 //*---------------------------------------------------------------------------- 3180 //* \fn AT91F_US1_CfgPIO 3181 //* \brief Configure PIO controllers to drive US1 signals 3182 //*---------------------------------------------------------------------------- AT91F_US1_CfgPIO(void)3183__inline void AT91F_US1_CfgPIO (void) 3184 { 3185 // Configure PIO controllers to periph mode 3186 AT91F_PIO_CfgPeriph( 3187 AT91C_BASE_PIOA, // PIO controller base address 3188 ((unsigned int) AT91C_PA21_RXD1 ) | 3189 ((unsigned int) AT91C_PA27_DTR1 ) | 3190 ((unsigned int) AT91C_PA26_DCD1 ) | 3191 ((unsigned int) AT91C_PA22_TXD1 ) | 3192 ((unsigned int) AT91C_PA24_RTS1 ) | 3193 ((unsigned int) AT91C_PA23_SCK1 ) | 3194 ((unsigned int) AT91C_PA28_DSR1 ) | 3195 ((unsigned int) AT91C_PA29_RI1 ) | 3196 ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A 3197 0); // Peripheral B 3198 } 3199 3200 //*---------------------------------------------------------------------------- 3201 //* \fn AT91F_US0_CfgPMC 3202 //* \brief Enable Peripheral clock in PMC for US0 3203 //*---------------------------------------------------------------------------- AT91F_US0_CfgPMC(void)3204__inline void AT91F_US0_CfgPMC (void) 3205 { 3206 AT91F_PMC_EnablePeriphClock( 3207 AT91C_BASE_PMC, // PIO controller base address 3208 ((unsigned int) 1 << AT91C_ID_US0)); 3209 } 3210 3211 //*---------------------------------------------------------------------------- 3212 //* \fn AT91F_US0_CfgPIO 3213 //* \brief Configure PIO controllers to drive US0 signals 3214 //*---------------------------------------------------------------------------- AT91F_US0_CfgPIO(void)3215__inline void AT91F_US0_CfgPIO (void) 3216 { 3217 // Configure PIO controllers to periph mode 3218 AT91F_PIO_CfgPeriph( 3219 AT91C_BASE_PIOA, // PIO controller base address 3220 ((unsigned int) AT91C_PA5_RXD0 ) | 3221 ((unsigned int) AT91C_PA6_TXD0 ) | 3222 ((unsigned int) AT91C_PA7_RTS0 ) | 3223 ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A 3224 ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B 3225 } 3226 3227 //*---------------------------------------------------------------------------- 3228 //* \fn AT91F_UDP_CfgPMC 3229 //* \brief Enable Peripheral clock in PMC for UDP 3230 //*---------------------------------------------------------------------------- AT91F_UDP_CfgPMC(void)3231__inline void AT91F_UDP_CfgPMC (void) 3232 { 3233 AT91F_PMC_EnablePeriphClock( 3234 AT91C_BASE_PMC, // PIO controller base address 3235 ((unsigned int) 1 << AT91C_ID_UDP)); 3236 } 3237 3238 //*---------------------------------------------------------------------------- 3239 //* \fn AT91F_AIC_CfgPMC 3240 //* \brief Enable Peripheral clock in PMC for AIC 3241 //*---------------------------------------------------------------------------- AT91F_AIC_CfgPMC(void)3242__inline void AT91F_AIC_CfgPMC (void) 3243 { 3244 AT91F_PMC_EnablePeriphClock( 3245 AT91C_BASE_PMC, // PIO controller base address 3246 ((unsigned int) 1 << AT91C_ID_IRQ0) | 3247 ((unsigned int) 1 << AT91C_ID_FIQ) | 3248 ((unsigned int) 1 << AT91C_ID_IRQ1)); 3249 } 3250 3251 //*---------------------------------------------------------------------------- 3252 //* \fn AT91F_AIC_CfgPIO 3253 //* \brief Configure PIO controllers to drive AIC signals 3254 //*---------------------------------------------------------------------------- AT91F_AIC_CfgPIO(void)3255__inline void AT91F_AIC_CfgPIO (void) 3256 { 3257 // Configure PIO controllers to periph mode 3258 AT91F_PIO_CfgPeriph( 3259 AT91C_BASE_PIOA, // PIO controller base address 3260 ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A 3261 ((unsigned int) AT91C_PA20_IRQ0 ) | 3262 ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B 3263 } 3264 3265 #endif // lib_AT91SAM7S64_H 3266
xref:
/Kernel-v10.6.2/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
(revision 01820d3ed93c735e5e8460a282971a7725fae44c)