1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33 /* *INDENT-OFF* */
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 /* *INDENT-ON* */
38
39 /*-----------------------------------------------------------
40 * Port specific definitions.
41 *
42 * The settings in this file configure FreeRTOS correctly for the
43 * given hardware and compiler.
44 *
45 * These settings should not be altered.
46 *-----------------------------------------------------------
47 */
48
49 /* IAR includes. */
50 #include <intrinsics.h>
51
52 /* Type definitions. */
53 #define portCHAR char
54 #define portFLOAT float
55 #define portDOUBLE double
56 #define portLONG long
57 #define portSHORT short
58 #define portSTACK_TYPE uint32_t
59 #define portBASE_TYPE long
60
61 typedef portSTACK_TYPE StackType_t;
62 typedef long BaseType_t;
63 typedef unsigned long UBaseType_t;
64
65 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
66 typedef uint16_t TickType_t;
67 #define portMAX_DELAY ( TickType_t ) 0xffff
68 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
69 typedef uint32_t TickType_t;
70 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
71
72 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
73 * not need to be guarded with a critical section. */
74 #define portTICK_TYPE_IS_ATOMIC 1
75 #else
76 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
77 #endif
78
79 /*-----------------------------------------------------------*/
80
81 /* MPU specific constants. */
82 #define portUSING_MPU_WRAPPERS 1
83 #define portPRIVILEGE_BIT ( 0x80000000UL )
84
85 #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
86 #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
87 #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
88 #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
89 #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
90 #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
91 #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
92
93 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
94 * Register (RASR). */
95 #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
96 #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
97
98 /* MPU settings that can be overriden in FreeRTOSConfig.h. */
99 #ifndef configTOTAL_MPU_REGIONS
100 /* Define to 8 for backward compatibility. */
101 #define configTOTAL_MPU_REGIONS ( 8UL )
102 #endif
103
104 /*
105 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
106 * memory type, and where necessary the cacheable and shareable properties
107 * of the memory region.
108 *
109 * The TEX, C, and B bits together indicate the memory type of the region,
110 * and:
111 * - For Normal memory, the cacheable properties of the region.
112 * - For Device memory, whether the region is shareable.
113 *
114 * For Normal memory regions, the S bit indicates whether the region is
115 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
116 *
117 * See the following two tables for setting TEX, S, C and B bits for
118 * unprivileged flash, privileged flash and privileged RAM regions.
119 *
120 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
121 | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
122 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
123 | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
124 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
125 | 000 | 0 | 1 | Device | Shared device | Shareable |
126 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
127 | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
128 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
129 | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
130 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
131 | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
132 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
133 | 001 | 0 | 1 | Reserved | Reserved | Reserved |
134 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
135 | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
136 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
137 | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
138 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
139 | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
140 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
141 | 010 | 0 | 1 | Reserved | Reserved | Reserved |
142 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
143 | 010 | 1 | X | Reserved | Reserved | Reserved |
144 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
145 | 011 | X | X | Reserved | Reserved | Reserved |
146 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
147 | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
148 | | | | | outer cacheability rules that must be exported on the | |
149 | | | | | bus. See the table below for the cacheability policy | |
150 | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
151 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
152 |
153 +-----------------------------------------+----------------------------------------+
154 | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
155 +-----------------------------------------+----------------------------------------+
156 | 00 | Non-cacheable |
157 +-----------------------------------------+----------------------------------------+
158 | 01 | Write-back, write and read allocate |
159 +-----------------------------------------+----------------------------------------+
160 | 10 | Write-through, no write allocate |
161 +-----------------------------------------+----------------------------------------+
162 | 11 | Write-back, no write allocate |
163 +-----------------------------------------+----------------------------------------+
164 */
165
166 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
167 * region. */
168 #ifndef configTEX_S_C_B_FLASH
169 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
170 #define configTEX_S_C_B_FLASH ( 0x07UL )
171 #endif
172
173 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
174 * region. */
175 #ifndef configTEX_S_C_B_SRAM
176 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
177 #define configTEX_S_C_B_SRAM ( 0x07UL )
178 #endif
179
180 #define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
181 #define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
182 #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
183 #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
184 #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
185 #define portFIRST_CONFIGURABLE_REGION ( 0UL )
186 #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
187 #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
188 #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
189
190 #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
191
192 typedef struct MPU_REGION_REGISTERS
193 {
194 uint32_t ulRegionBaseAddress;
195 uint32_t ulRegionAttribute;
196 } xMPU_REGION_REGISTERS;
197
198 typedef struct MPU_REGION_SETTINGS
199 {
200 uint32_t ulRegionStartAddress;
201 uint32_t ulRegionEndAddress;
202 uint32_t ulRegionPermissions;
203 } xMPU_REGION_SETTINGS;
204
205 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
206
207 #ifndef configSYSTEM_CALL_STACK_SIZE
208 #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
209 #endif
210
211 typedef struct SYSTEM_CALL_STACK_INFO
212 {
213 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
214 uint32_t * pulSystemCallStack;
215 uint32_t * pulTaskStack;
216 uint32_t ulLinkRegisterAtSystemCallEntry;
217 } xSYSTEM_CALL_STACK_INFO;
218
219 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
220
221 #define MAX_CONTEXT_SIZE ( 52 )
222
223 /* Size of an Access Control List (ACL) entry in bits. */
224 #define portACL_ENTRY_SIZE_BITS ( 32U )
225
226 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
227 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
228 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
229
230 typedef struct MPU_SETTINGS
231 {
232 xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
233 xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
234 uint32_t ulContext[ MAX_CONTEXT_SIZE ];
235 uint32_t ulTaskFlags;
236
237 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
238 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
239 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
240 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
241 #endif
242 #endif
243 } xMPU_SETTINGS;
244
245 /* Architecture specifics. */
246 #define portSTACK_GROWTH ( -1 )
247 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
248 #define portBYTE_ALIGNMENT 8
249 /*-----------------------------------------------------------*/
250
251 /* SVC numbers for various services. */
252 #define portSVC_START_SCHEDULER 100
253 #define portSVC_YIELD 101
254 #define portSVC_RAISE_PRIVILEGE 102
255 #define portSVC_SYSTEM_CALL_EXIT 103
256
257 /* Scheduler utilities. */
258
259 #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
260 #define portYIELD_WITHIN_API() \
261 { \
262 /* Set a PendSV to request a context switch. */ \
263 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
264 __DSB(); \
265 __ISB(); \
266 }
267
268 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
269 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
270 #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 )
271 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
272 /*-----------------------------------------------------------*/
273
274 /* Architecture specific optimisations. */
275 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
276 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
277 #endif
278
279 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
280
281 /* Check the configuration. */
282 #if ( configMAX_PRIORITIES > 32 )
283 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
284 #endif
285
286 /* Store/clear the ready priorities in a bit map. */
287 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
288 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
289
290 /*-----------------------------------------------------------*/
291
292 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
293
294 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
295 /*-----------------------------------------------------------*/
296
297 /* Critical section management. */
298 extern void vPortEnterCritical( void );
299 extern void vPortExitCritical( void );
300
301 #if( configENABLE_ERRATA_837070_WORKAROUND == 1 )
302 #define portDISABLE_INTERRUPTS() \
303 { \
304 __disable_interrupt(); \
305 __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
306 __DSB(); \
307 __ISB(); \
308 __enable_interrupt(); \
309 }
310 #else
311 #define portDISABLE_INTERRUPTS() \
312 { \
313 __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
314 __DSB(); \
315 __ISB(); \
316 }
317 #endif
318
319 #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
320 #define portENTER_CRITICAL() vPortEnterCritical()
321 #define portEXIT_CRITICAL() vPortExitCritical()
322 #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS()
323 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x )
324 /*-----------------------------------------------------------*/
325
326 /* Task function macros as described on the FreeRTOS.org WEB site. These are
327 * not necessary for to use this port. They are defined so the common demo files
328 * (which build with all the ports) will build. */
329 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
330 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
331 /*-----------------------------------------------------------*/
332
333 #ifdef configASSERT
334 void vPortValidateInterruptPriority( void );
335 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
336 #endif
337
338 /* portNOP() is not required by this port. */
339 #define portNOP()
340
341 #define portINLINE __inline
342
343 #ifndef portFORCE_INLINE
344 #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
345 #endif
346
347 /*-----------------------------------------------------------*/
348
xPortIsInsideInterrupt(void)349 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
350 {
351 uint32_t ulCurrentInterrupt;
352 BaseType_t xReturn;
353
354 /* Obtain the number of the currently executing interrupt. */
355 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
356
357 if( ulCurrentInterrupt == 0 )
358 {
359 xReturn = pdFALSE;
360 }
361 else
362 {
363 xReturn = pdTRUE;
364 }
365
366 return xReturn;
367 }
368
369
370 /*-----------------------------------------------------------*/
371
372 extern BaseType_t xIsPrivileged( void );
373 extern void vResetPrivilege( void );
374
375 /**
376 * @brief Checks whether or not the processor is privileged.
377 *
378 * @return 1 if the processor is already privileged, 0 otherwise.
379 */
380 #define portIS_PRIVILEGED() xIsPrivileged()
381
382 /**
383 * @brief Raise an SVC request to raise privilege.
384 */
385 #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
386
387 /**
388 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
389 * register.
390 */
391 #define portRESET_PRIVILEGE() vResetPrivilege()
392 /*-----------------------------------------------------------*/
393
394 extern BaseType_t xPortIsTaskPrivileged( void );
395
396 /**
397 * @brief Checks whether or not the calling task is privileged.
398 *
399 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
400 */
401 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
402 /*-----------------------------------------------------------*/
403
404 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
405 #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
406 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
407 #endif
408 /*-----------------------------------------------------------*/
409
410 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
411 * the source code because to do so would cause other compilers to generate
412 * warnings. */
413 #pragma diag_suppress=Pe191
414 #pragma diag_suppress=Pa082
415 #pragma diag_suppress=Be006
416 /*-----------------------------------------------------------*/
417
418 /* *INDENT-OFF* */
419 #ifdef __cplusplus
420 }
421 #endif
422 /* *INDENT-ON* */
423
424 #endif /* PORTMACRO_H */
425
