1/* 2 * FreeRTOS Kernel V10.6.2 3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * https://www.FreeRTOS.org 25 * https://github.com/FreeRTOS 26 * 27 */ 28/* Including FreeRTOSConfig.h here will cause build errors if the header file 29contains code not understood by the assembler - for example the 'extern' keyword. 30To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so 31the code is included in C files but excluded by the preprocessor in assembly 32files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ 33#include "FreeRTOSConfig.h" 34 35/* System call numbers includes. */ 36#include "mpu_syscall_numbers.h" 37 38#ifndef configUSE_MPU_WRAPPERS_V1 39 #define configUSE_MPU_WRAPPERS_V1 0 40#endif 41 42 EXTERN pxCurrentTCB 43 EXTERN vTaskSwitchContext 44 EXTERN vPortSVCHandler_C 45#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) 46 EXTERN vSystemCallEnter 47 EXTERN vSystemCallExit 48#endif 49 50 PUBLIC xIsPrivileged 51 PUBLIC vResetPrivilege 52 PUBLIC vRestoreContextOfFirstTask 53 PUBLIC vRaisePrivilege 54 PUBLIC vStartFirstTask 55 PUBLIC ulSetInterruptMask 56 PUBLIC vClearInterruptMask 57 PUBLIC PendSV_Handler 58 PUBLIC SVC_Handler 59/*-----------------------------------------------------------*/ 60 61/*---------------- Unprivileged Functions -------------------*/ 62 63/*-----------------------------------------------------------*/ 64 65 SECTION .text:CODE:NOROOT(2) 66 THUMB 67/*-----------------------------------------------------------*/ 68 69xIsPrivileged: 70 mrs r0, control /* r0 = CONTROL. */ 71 tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ 72 ite ne 73 movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ 74 moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ 75 bx lr /* Return. */ 76/*-----------------------------------------------------------*/ 77 78vResetPrivilege: 79 mrs r0, control /* r0 = CONTROL. */ 80 orr r0, r0, #1 /* r0 = r0 | 1. */ 81 msr control, r0 /* CONTROL = r0. */ 82 bx lr /* Return to the caller. */ 83/*-----------------------------------------------------------*/ 84 85/*----------------- Privileged Functions --------------------*/ 86 87/*-----------------------------------------------------------*/ 88 89 SECTION privileged_functions:CODE:NOROOT(2) 90 THUMB 91/*-----------------------------------------------------------*/ 92 93#if ( configENABLE_MPU == 1 ) 94 95vRestoreContextOfFirstTask: 96 program_mpu_first_task: 97 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 98 ldr r0, [r2] /* r0 = pxCurrentTCB. */ 99 100 dmb /* Complete outstanding transfers before disabling MPU. */ 101 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 102 ldr r2, [r1] /* Read the value of MPU_CTRL. */ 103 bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ 104 str r2, [r1] /* Disable MPU. */ 105 106 adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ 107 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ 108 ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ 109 str r1, [r2] /* Program MAIR0. */ 110 111 adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ 112 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ 113 ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ 114 115 movs r3, #4 /* r3 = 4. */ 116 str r3, [r1] /* Program RNR = 4. */ 117 ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ 118 stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ 119 120 #if ( configTOTAL_MPU_REGIONS == 16 ) 121 movs r3, #8 /* r3 = 8. */ 122 str r3, [r1] /* Program RNR = 8. */ 123 ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ 124 stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ 125 movs r3, #12 /* r3 = 12. */ 126 str r3, [r1] /* Program RNR = 12. */ 127 ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ 128 stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ 129 #endif /* configTOTAL_MPU_REGIONS == 16 */ 130 131 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 132 ldr r2, [r1] /* Read the value of MPU_CTRL. */ 133 orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ 134 str r2, [r1] /* Enable MPU. */ 135 dsb /* Force memory writes before continuing. */ 136 137 restore_context_first_task: 138 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 139 ldr r0, [r2] /* r0 = pxCurrentTCB.*/ 140 ldr r1, [r0] /* r1 = Location of saved context in TCB. */ 141 142 restore_special_regs_first_task: 143 ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ 144 msr psp, r2 145 msr psplim, r3 146 msr control, r4 147 148 restore_general_regs_first_task: 149 ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ 150 stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ 151 ldmdb r1!, {r4-r11} /* r4-r11 restored. */ 152 153 restore_context_done_first_task: 154 str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ 155 mov r0, #0 156 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ 157 bx lr 158 159#else /* configENABLE_MPU */ 160 161vRestoreContextOfFirstTask: 162 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 163 ldr r1, [r2] /* Read pxCurrentTCB. */ 164 ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ 165 166 ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ 167 msr psplim, r1 /* Set this task's PSPLIM value. */ 168 movs r1, #2 /* r1 = 2. */ 169 msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ 170 adds r0, #32 /* Discard everything up to r0. */ 171 msr psp, r0 /* This is now the new top of stack to use in the task. */ 172 isb 173 mov r0, #0 174 msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ 175 bx r2 /* Finally, branch to EXC_RETURN. */ 176 177#endif /* configENABLE_MPU */ 178/*-----------------------------------------------------------*/ 179 180vRaisePrivilege: 181 mrs r0, control /* Read the CONTROL register. */ 182 bic r0, r0, #1 /* Clear the bit 0. */ 183 msr control, r0 /* Write back the new CONTROL value. */ 184 bx lr /* Return to the caller. */ 185/*-----------------------------------------------------------*/ 186 187vStartFirstTask: 188 ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ 189 ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ 190 ldr r0, [r0] /* The first entry in vector table is stack pointer. */ 191 msr msp, r0 /* Set the MSP back to the start of the stack. */ 192 cpsie i /* Globally enable interrupts. */ 193 cpsie f 194 dsb 195 isb 196 svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ 197/*-----------------------------------------------------------*/ 198 199ulSetInterruptMask: 200 mrs r0, basepri /* r0 = basepri. Return original basepri value. */ 201 mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY 202 msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ 203 dsb 204 isb 205 bx lr /* Return. */ 206/*-----------------------------------------------------------*/ 207 208vClearInterruptMask: 209 msr basepri, r0 /* basepri = ulMask. */ 210 dsb 211 isb 212 bx lr /* Return. */ 213/*-----------------------------------------------------------*/ 214 215#if ( configENABLE_MPU == 1 ) 216 217PendSV_Handler: 218 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 219 ldr r0, [r2] /* r0 = pxCurrentTCB. */ 220 ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ 221 mrs r2, psp /* r2 = PSP. */ 222 223 save_general_regs: 224 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) 225 add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ 226 tst lr, #0x10 227 ittt eq 228 vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ 229 vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ 230 vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ 231 sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ 232 #endif /* configENABLE_FPU || configENABLE_MVE */ 233 234 stmia r1!, {r4-r11} /* Store r4-r11. */ 235 ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ 236 stmia r1!, {r4-r11} /* Store the hardware saved context. */ 237 238 save_special_regs: 239 mrs r3, psplim /* r3 = PSPLIM. */ 240 mrs r4, control /* r4 = CONTROL. */ 241 stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ 242 str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ 243 244 select_next_task: 245 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY 246 msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ 247 dsb 248 isb 249 bl vTaskSwitchContext 250 mov r0, #0 /* r0 = 0. */ 251 msr basepri, r0 /* Enable interrupts. */ 252 253 program_mpu: 254 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 255 ldr r0, [r2] /* r0 = pxCurrentTCB. */ 256 257 dmb /* Complete outstanding transfers before disabling MPU. */ 258 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 259 ldr r2, [r1] /* Read the value of MPU_CTRL. */ 260 bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ 261 str r2, [r1] /* Disable MPU. */ 262 263 adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ 264 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ 265 ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ 266 str r1, [r2] /* Program MAIR0. */ 267 268 adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ 269 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ 270 ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ 271 272 movs r3, #4 /* r3 = 4. */ 273 str r3, [r1] /* Program RNR = 4. */ 274 ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ 275 stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ 276 277 #if ( configTOTAL_MPU_REGIONS == 16 ) 278 movs r3, #8 /* r3 = 8. */ 279 str r3, [r1] /* Program RNR = 8. */ 280 ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ 281 stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ 282 movs r3, #12 /* r3 = 12. */ 283 str r3, [r1] /* Program RNR = 12. */ 284 ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ 285 stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ 286 #endif /* configTOTAL_MPU_REGIONS == 16 */ 287 288 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 289 ldr r2, [r1] /* Read the value of MPU_CTRL. */ 290 orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ 291 str r2, [r1] /* Enable MPU. */ 292 dsb /* Force memory writes before continuing. */ 293 294 restore_context: 295 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 296 ldr r0, [r2] /* r0 = pxCurrentTCB.*/ 297 ldr r1, [r0] /* r1 = Location of saved context in TCB. */ 298 299 restore_special_regs: 300 ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ 301 msr psp, r2 302 msr psplim, r3 303 msr control, r4 304 305 restore_general_regs: 306 ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ 307 stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ 308 ldmdb r1!, {r4-r11} /* r4-r11 restored. */ 309 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) 310 tst lr, #0x10 311 ittt eq 312 vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ 313 vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ 314 vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ 315 #endif /* configENABLE_FPU || configENABLE_MVE */ 316 317 restore_context_done: 318 str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ 319 bx lr 320 321#else /* configENABLE_MPU */ 322 323PendSV_Handler: 324 mrs r0, psp /* Read PSP in r0. */ 325#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) 326 tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ 327 it eq 328 vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ 329#endif /* configENABLE_FPU || configENABLE_MVE */ 330 331 mrs r2, psplim /* r2 = PSPLIM. */ 332 mov r3, lr /* r3 = LR/EXC_RETURN. */ 333 stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ 334 335 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 336 ldr r1, [r2] /* Read pxCurrentTCB. */ 337 str r0, [r1] /* Save the new top of stack in TCB. */ 338 339 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY 340 msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ 341 dsb 342 isb 343 bl vTaskSwitchContext 344 mov r0, #0 /* r0 = 0. */ 345 msr basepri, r0 /* Enable interrupts. */ 346 347 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 348 ldr r1, [r2] /* Read pxCurrentTCB. */ 349 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ 350 351 ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ 352 353#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) 354 tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ 355 it eq 356 vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ 357#endif /* configENABLE_FPU || configENABLE_MVE */ 358 359 msr psplim, r2 /* Restore the PSPLIM register value for the task. */ 360 msr psp, r0 /* Remember the new top of stack for the task. */ 361 bx r3 362 363#endif /* configENABLE_MPU */ 364/*-----------------------------------------------------------*/ 365 366#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) 367 368SVC_Handler: 369 tst lr, #4 370 ite eq 371 mrseq r0, msp 372 mrsne r0, psp 373 374 ldr r1, [r0, #24] 375 ldrb r2, [r1, #-2] 376 cmp r2, #NUM_SYSTEM_CALLS 377 blt syscall_enter 378 cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ 379 beq syscall_exit 380 b vPortSVCHandler_C 381 382 syscall_enter: 383 mov r1, lr 384 b vSystemCallEnter 385 386 syscall_exit: 387 mov r1, lr 388 b vSystemCallExit 389 390#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ 391 392SVC_Handler: 393 tst lr, #4 394 ite eq 395 mrseq r0, msp 396 mrsne r0, psp 397 b vPortSVCHandler_C 398 399#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ 400/*-----------------------------------------------------------*/ 401 402 END 403
xref:
/Kernel-v10.6.2/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
(revision ef7b253b56c9788077f5ecd6c9deb4021923d646)