1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31
32 /* Scheduler includes. */
33 #include "FreeRTOS.h"
34 #include "task.h"
35
36 /* The critical nesting value is initialised to a non zero value to ensure
37 interrupts don't accidentally become enabled before the scheduler is started. */
38 #define portINITIAL_CRITICAL_NESTING (( uint16_t ) 10)
39
40 /* Initial PSW value allocated to a newly created task.
41 * 1100011000000000
42 * ||||||||-------------- Fill byte
43 * |||||||--------------- Carry Flag cleared
44 * |||||----------------- In-service priority Flags set to low level
45 * ||||------------------ Register bank Select 0 Flag cleared
46 * |||------------------- Auxiliary Carry Flag cleared
47 * ||-------------------- Register bank Select 1 Flag cleared
48 * |--------------------- Zero Flag set
49 * ---------------------- Global Interrupt Flag set (enabled)
50 */
51 #define portPSW (0xc6UL)
52
53 /* We require the address of the pxCurrentTCB variable, but don't want to know
54 any details of its type. */
55 typedef void TCB_t;
56 extern volatile TCB_t * volatile pxCurrentTCB;
57
58 /* Most ports implement critical sections by placing the interrupt flags on
59 the stack before disabling interrupts. Exiting the critical section is then
60 simply a case of popping the flags from the stack. As 78K0 IAR does not use
61 a frame pointer this cannot be done as modifying the stack will clobber all
62 the stack variables. Instead each task maintains a count of the critical
63 section nesting depth. Each time a critical section is entered the count is
64 incremented. Each time a critical section is left the count is decremented -
65 with interrupts only being re-enabled if the count is zero.
66
67 usCriticalNesting will get set to zero when the scheduler starts, but must
68 not be initialised to zero as this will cause problems during the startup
69 sequence. */
70 volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
71 /*-----------------------------------------------------------*/
72
73 /*
74 * Sets up the periodic ISR used for the RTOS tick.
75 */
76 static void prvSetupTimerInterrupt( void );
77 /*-----------------------------------------------------------*/
78
79 /*
80 * Initialise the stack of a task to look exactly as if a call to
81 * portSAVE_CONTEXT had been called.
82 *
83 * See the header file portable.h.
84 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)85 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
86 {
87 uint32_t *pulLocal;
88
89 #if configMEMORY_MODE == 1
90 {
91 /* Parameters are passed in on the stack, and written using a 32bit value
92 hence a space is left for the second two bytes. */
93 pxTopOfStack--;
94
95 /* Write in the parameter value. */
96 pulLocal = ( uint32_t * ) pxTopOfStack;
97 *pulLocal = ( uint32_t ) pvParameters;
98 pxTopOfStack--;
99
100 /* These values are just spacers. The return address of the function
101 would normally be written here. */
102 *pxTopOfStack = ( StackType_t ) 0xcdcd;
103 pxTopOfStack--;
104 *pxTopOfStack = ( StackType_t ) 0xcdcd;
105 pxTopOfStack--;
106
107 /* The start address / PSW value is also written in as a 32bit value,
108 so leave a space for the second two bytes. */
109 pxTopOfStack--;
110
111 /* Task function start address combined with the PSW. */
112 pulLocal = ( uint32_t * ) pxTopOfStack;
113 *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
114 pxTopOfStack--;
115
116 /* An initial value for the AX register. */
117 *pxTopOfStack = ( StackType_t ) 0x1111;
118 pxTopOfStack--;
119 }
120 #else
121 {
122 /* Task function address is written to the stack first. As it is
123 written as a 32bit value a space is left on the stack for the second
124 two bytes. */
125 pxTopOfStack--;
126
127 /* Task function start address combined with the PSW. */
128 pulLocal = ( uint32_t * ) pxTopOfStack;
129 *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
130 pxTopOfStack--;
131
132 /* The parameter is passed in AX. */
133 *pxTopOfStack = ( StackType_t ) pvParameters;
134 pxTopOfStack--;
135 }
136 #endif
137
138 /* An initial value for the HL register. */
139 *pxTopOfStack = ( StackType_t ) 0x2222;
140 pxTopOfStack--;
141
142 /* CS and ES registers. */
143 *pxTopOfStack = ( StackType_t ) 0x0F00;
144 pxTopOfStack--;
145
146 /* Finally the remaining general purpose registers DE and BC */
147 *pxTopOfStack = ( StackType_t ) 0xDEDE;
148 pxTopOfStack--;
149 *pxTopOfStack = ( StackType_t ) 0xBCBC;
150 pxTopOfStack--;
151
152 /* Finally the critical section nesting count is set to zero when the task
153 first starts. */
154 *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
155
156 /* Return a pointer to the top of the stack we have generated so this can
157 be stored in the task control block for the task. */
158 return pxTopOfStack;
159 }
160 /*-----------------------------------------------------------*/
161
xPortStartScheduler(void)162 BaseType_t xPortStartScheduler( void )
163 {
164 /* Setup the hardware to generate the tick. Interrupts are disabled when
165 this function is called. */
166 prvSetupTimerInterrupt();
167
168 /* Restore the context of the first task that is going to run. */
169 vPortStart();
170
171 /* Should not get here as the tasks are now running! */
172 return pdTRUE;
173 }
174 /*-----------------------------------------------------------*/
175
vPortEndScheduler(void)176 void vPortEndScheduler( void )
177 {
178 /* It is unlikely that the 78K0R port will get stopped. If required simply
179 disable the tick interrupt here. */
180 }
181 /*-----------------------------------------------------------*/
182
prvSetupTimerInterrupt(void)183 static void prvSetupTimerInterrupt( void )
184 {
185 /* Setup channel 5 of the TAU to generate the tick interrupt. */
186
187 /* First the Timer Array Unit has to be enabled. */
188 TAU0EN = 1;
189
190 /* To configure the Timer Array Unit all Channels have to first be stopped. */
191 TT0 = 0xff;
192
193 /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
194 priority. */
195 TMMK05 = 1;
196
197 /* Clear Timer Array Unit Channel 5 interrupt flag. */
198 TMIF05 = 0;
199
200 /* Set Timer Array Unit Channel 5 interrupt priority */
201 TMPR005 = 0;
202 TMPR105 = 0;
203
204 /* Set Timer Array Unit Channel 5 Mode as interval timer. */
205 TMR05 = 0x0000;
206
207 /* Set the compare match value according to the tick rate we want. */
208 TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
209
210 /* Set Timer Array Unit Channel 5 output mode */
211 TOM0 &= ~0x0020;
212
213 /* Set Timer Array Unit Channel 5 output level */
214 TOL0 &= ~0x0020;
215
216 /* Set Timer Array Unit Channel 5 output enable */
217 TOE0 &= ~0x0020;
218
219 /* Interrupt of Timer Array Unit Channel 5 enabled */
220 TMMK05 = 0;
221
222 /* Start Timer Array Unit Channel 5.*/
223 TS0 |= 0x0020;
224 }
225 /*-----------------------------------------------------------*/
226
