1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the MicroBlaze port.
31 *----------------------------------------------------------*/
32
33
34 /* Scheduler includes. */
35 #include "FreeRTOS.h"
36 #include "task.h"
37
38 /* Standard includes. */
39 #include <string.h>
40
41 /* Hardware includes. */
42 #include <xintc_i.h>
43 #include <xil_exception.h>
44 #include <microblaze_exceptions_g.h>
45
46 /* Tasks are started with a critical section nesting of 0 - however, prior to
47 the scheduler being commenced interrupts should not be enabled, so the critical
48 nesting variable is initialised to a non-zero value. */
49 #define portINITIAL_NESTING_VALUE ( 0xff )
50
51 /* The bit within the MSR register that enabled/disables interrupts and
52 exceptions respectively. */
53 #define portMSR_IE ( 0x02U )
54 #define portMSR_EE ( 0x100U )
55
56 /* If the floating point unit is included in the MicroBlaze build, then the
57 FSR register is saved as part of the task context. portINITIAL_FSR is the value
58 given to the FSR register when the initial context is set up for a task being
59 created. */
60 #define portINITIAL_FSR ( 0U )
61
62 /*-----------------------------------------------------------*/
63
64 /*
65 * Initialise the interrupt controller instance.
66 */
67 static int32_t prvInitialiseInterruptController( void );
68
69 /* Ensure the interrupt controller instance variable is initialised before it is
70 * used, and that the initialisation only happens once.
71 */
72 static int32_t prvEnsureInterruptControllerIsInitialised( void );
73
74 /*-----------------------------------------------------------*/
75
76 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
77 maintains its own count, so this variable is saved as part of the task
78 context. */
79 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
80
81 /* This port uses a separate stack for interrupts. This prevents the stack of
82 every task needing to be large enough to hold an entire interrupt stack on top
83 of the task stack. */
84 uint32_t *pulISRStack;
85
86 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
87 get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
88 handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
89 will call vTaskSwitchContext() to ensure the task that runs immediately after
90 the interrupt exists is the highest priority task that is able to run. This is
91 an unusual mechanism, but is used for this port because a single interrupt can
92 cause the servicing of multiple peripherals - and it is inefficient to call
93 vTaskSwitchContext() multiple times as each peripheral is serviced. */
94 volatile uint32_t ulTaskSwitchRequested = 0UL;
95
96 /* The instance of the interrupt controller used by this port. This is required
97 by the Xilinx library API functions. */
98 static XIntc xInterruptControllerInstance;
99
100 /*-----------------------------------------------------------*/
101
102 /*
103 * Initialise the stack of a task to look exactly as if a call to
104 * portSAVE_CONTEXT had been made.
105 *
106 * See the portable.h header file.
107 */
108 #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
pxPortInitialiseStack(StackType_t * pxTopOfStack,StackType_t * pxEndOfStack,TaskFunction_t pxCode,void * pvParameters)109 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters )
110 #else
111 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
112 #endif
113 {
114 extern void * _SDA2_BASE_;
115 extern void * _SDA_BASE_;
116 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
117 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
118 extern void _start1( void );
119
120 /* Place a few bytes of known values on the bottom of the stack.
121 This is essential for the Microblaze port and these lines must
122 not be omitted. */
123 *pxTopOfStack = ( StackType_t ) 0x00000000;
124 pxTopOfStack--;
125 *pxTopOfStack = ( StackType_t ) 0x00000000;
126 pxTopOfStack--;
127 *pxTopOfStack = ( StackType_t ) 0x00000000;
128 pxTopOfStack--;
129
130 #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
131 /* Store the stack limits. */
132 *pxTopOfStack = (StackType_t) (pxTopOfStack + 3);
133 pxTopOfStack--;
134 *pxTopOfStack = (StackType_t) pxEndOfStack;
135 pxTopOfStack--;
136 #endif
137
138 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
139 /* The FSR value placed in the initial task context is just 0. */
140 *pxTopOfStack = portINITIAL_FSR;
141 pxTopOfStack--;
142 #endif
143
144 /* The MSR value placed in the initial task context should have interrupts
145 disabled. Each task will enable interrupts automatically when it enters
146 the running state for the first time. */
147 *pxTopOfStack = mfmsr() & ~portMSR_IE;
148
149 #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
150 {
151 /* Ensure exceptions are enabled for the task. */
152 *pxTopOfStack |= portMSR_EE;
153 }
154 #endif
155
156 pxTopOfStack--;
157
158 /* First stack an initial value for the critical section nesting. This
159 is initialised to zero. */
160 *pxTopOfStack = ( StackType_t ) 0x00;
161
162 /* R0 is always zero. */
163 /* R1 is the SP. */
164
165 /* Place an initial value for all the general purpose registers. */
166 pxTopOfStack--;
167 *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
168 pxTopOfStack--;
169 *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
170 pxTopOfStack--;
171 *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
172 pxTopOfStack--;
173 *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
174
175 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
176 pxTopOfStack--;
177 *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
178 pxTopOfStack--;
179 *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
180 pxTopOfStack--;
181 *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
182 pxTopOfStack--;
183 *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
184 pxTopOfStack--;
185 *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
186 pxTopOfStack--;
187 *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
188 pxTopOfStack--;
189 *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
190 pxTopOfStack--;
191 #else
192 pxTopOfStack-= 8;
193 #endif
194
195 *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
196 pxTopOfStack--;
197 *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
198 pxTopOfStack--;
199 *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
200
201 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
202 pxTopOfStack--;
203 *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
204 pxTopOfStack--;
205 *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
206 pxTopOfStack--;
207 *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
208 pxTopOfStack--;
209 #else
210 pxTopOfStack -= 4;
211 #endif
212
213 *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
214
215 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
216 pxTopOfStack--;
217 *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
218 pxTopOfStack--;
219 *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
220 pxTopOfStack--;
221 *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
222 pxTopOfStack--;
223 *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
224 pxTopOfStack--;
225 *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
226 pxTopOfStack--;
227 *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
228 pxTopOfStack--;
229 *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
230 pxTopOfStack--;
231 *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
232 pxTopOfStack--;
233 *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
234 pxTopOfStack--;
235 *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
236 pxTopOfStack--;
237 *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
238 pxTopOfStack--;
239 *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
240 pxTopOfStack--;
241 #else
242 pxTopOfStack -= 13;
243 #endif
244
245 /* Return a pointer to the top of the stack that has been generated so this
246 can be stored in the task control block for the task. */
247 return pxTopOfStack;
248 }
249 /*-----------------------------------------------------------*/
250
xPortStartScheduler(void)251 BaseType_t xPortStartScheduler( void )
252 {
253 extern void ( vPortStartFirstTask )( void );
254 extern uint32_t _stack[];
255
256 /* Setup the hardware to generate the tick. Interrupts are disabled when
257 this function is called.
258
259 This port uses an application defined callback function to install the tick
260 interrupt handler because the kernel will run on lots of different
261 MicroBlaze and FPGA configurations - not all of which will have the same
262 timer peripherals defined or available. An example definition of
263 vApplicationSetupTimerInterrupt() is provided in the official demo
264 application that accompanies this port. */
265 vApplicationSetupTimerInterrupt();
266
267 /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
268 pulISRStack = ( uint32_t * ) _stack;
269
270 /* Ensure there is enough space for the functions called from the interrupt
271 service routines to write back into the stack frame of the caller. */
272 pulISRStack -= 2;
273
274 /* Restore the context of the first task that is going to run. From here
275 on, the created tasks will be executing. */
276 vPortStartFirstTask();
277
278 /* Should not get here as the tasks are now running! */
279 return pdFALSE;
280 }
281 /*-----------------------------------------------------------*/
282
vPortEndScheduler(void)283 void vPortEndScheduler( void )
284 {
285 /* Not implemented in ports where there is nothing to return to.
286 Artificially force an assert. */
287 configASSERT( uxCriticalNesting == 1000UL );
288 }
289 /*-----------------------------------------------------------*/
290
291 /*
292 * Manual context switch called by portYIELD or taskYIELD.
293 */
vPortYield(void)294 void vPortYield( void )
295 {
296 extern void VPortYieldASM( void );
297
298 /* Perform the context switch in a critical section to assure it is
299 not interrupted by the tick ISR. It is not a problem to do this as
300 each task maintains its own interrupt status. */
301 portENTER_CRITICAL();
302 {
303 /* Jump directly to the yield function to ensure there is no
304 compiler generated prologue code. */
305 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
306 "or r0, r0, r0 \n\t" );
307 }
308 portEXIT_CRITICAL();
309 }
310 /*-----------------------------------------------------------*/
311
vPortEnableInterrupt(uint8_t ucInterruptID)312 void vPortEnableInterrupt( uint8_t ucInterruptID )
313 {
314 int32_t lReturn;
315
316 /* An API function is provided to enable an interrupt in the interrupt
317 controller because the interrupt controller instance variable is private
318 to this file. */
319 lReturn = prvEnsureInterruptControllerIsInitialised();
320 if( lReturn == pdPASS )
321 {
322 /* Critical section protects read/modify/writer operation inside
323 XIntc_Enable(). */
324 portENTER_CRITICAL();
325 {
326 XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
327 }
328 portEXIT_CRITICAL();
329 }
330
331 configASSERT( lReturn == pdPASS );
332 }
333 /*-----------------------------------------------------------*/
334
vPortDisableInterrupt(uint8_t ucInterruptID)335 void vPortDisableInterrupt( uint8_t ucInterruptID )
336 {
337 int32_t lReturn;
338
339 /* An API function is provided to disable an interrupt in the interrupt
340 controller because the interrupt controller instance variable is private
341 to this file. */
342 lReturn = prvEnsureInterruptControllerIsInitialised();
343
344 if( lReturn == pdPASS )
345 {
346 XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
347 }
348
349 configASSERT( lReturn == pdPASS );
350 }
351 /*-----------------------------------------------------------*/
352
xPortInstallInterruptHandler(uint8_t ucInterruptID,XInterruptHandler pxHandler,void * pvCallBackRef)353 BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
354 {
355 int32_t lReturn;
356
357 /* An API function is provided to install an interrupt handler because the
358 interrupt controller instance variable is private to this file. */
359
360 lReturn = prvEnsureInterruptControllerIsInitialised();
361
362 if( lReturn == pdPASS )
363 {
364 lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
365 }
366
367 if( lReturn == XST_SUCCESS )
368 {
369 lReturn = pdPASS;
370 }
371
372 configASSERT( lReturn == pdPASS );
373
374 return lReturn;
375 }
376 /*-----------------------------------------------------------*/
377
vPortRemoveInterruptHandler(uint8_t ucInterruptID)378 void vPortRemoveInterruptHandler( uint8_t ucInterruptID )
379 {
380 int32_t lReturn;
381
382 /* An API function is provided to remove an interrupt handler because the
383 interrupt controller instance variable is private to this file. */
384
385 lReturn = prvEnsureInterruptControllerIsInitialised();
386
387 if( lReturn == pdPASS )
388 {
389 XIntc_Disconnect( &xInterruptControllerInstance, ucInterruptID );
390 }
391
392 configASSERT( lReturn == pdPASS );
393 }
394 /*-----------------------------------------------------------*/
395
prvEnsureInterruptControllerIsInitialised(void)396 static int32_t prvEnsureInterruptControllerIsInitialised( void )
397 {
398 static int32_t lInterruptControllerInitialised = pdFALSE;
399 int32_t lReturn;
400
401 /* Ensure the interrupt controller instance variable is initialised before
402 it is used, and that the initialisation only happens once. */
403 if( lInterruptControllerInitialised != pdTRUE )
404 {
405 lReturn = prvInitialiseInterruptController();
406
407 if( lReturn == pdPASS )
408 {
409 lInterruptControllerInitialised = pdTRUE;
410 }
411 }
412 else
413 {
414 lReturn = pdPASS;
415 }
416
417 return lReturn;
418 }
419 /*-----------------------------------------------------------*/
420
421 /*
422 * Handler for the timer interrupt. This is the handler that the application
423 * defined callback function vApplicationSetupTimerInterrupt() should install.
424 */
vPortTickISR(void * pvUnused)425 void vPortTickISR( void *pvUnused )
426 {
427 extern void vApplicationClearTimerInterrupt( void );
428
429 /* Ensure the unused parameter does not generate a compiler warning. */
430 ( void ) pvUnused;
431
432 /* This port uses an application defined callback function to clear the tick
433 interrupt because the kernel will run on lots of different MicroBlaze and
434 FPGA configurations - not all of which will have the same timer peripherals
435 defined or available. An example definition of
436 vApplicationClearTimerInterrupt() is provided in the official demo
437 application that accompanies this port. */
438 vApplicationClearTimerInterrupt();
439
440 /* Increment the RTOS tick - this might cause a task to unblock. */
441 if( xTaskIncrementTick() != pdFALSE )
442 {
443 /* Force vTaskSwitchContext() to be called as the interrupt exits. */
444 ulTaskSwitchRequested = 1;
445 }
446 }
447 /*-----------------------------------------------------------*/
448
prvInitialiseInterruptController(void)449 static int32_t prvInitialiseInterruptController( void )
450 {
451 int32_t lStatus;
452
453 lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
454
455 if( lStatus == XST_SUCCESS )
456 {
457 /* Initialise the exception table. */
458 Xil_ExceptionInit();
459
460 /* Service all pending interrupts each time the handler is entered. */
461 XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
462
463 /* Install exception handlers if the MicroBlaze is configured to handle
464 exceptions, and the application defined constant
465 configINSTALL_EXCEPTION_HANDLERS is set to 1. */
466 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
467 {
468 vPortExceptionsInstallHandlers();
469 }
470 #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
471
472 /* Start the interrupt controller. Interrupts are enabled when the
473 scheduler starts. */
474 lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
475
476 if( lStatus == XST_SUCCESS )
477 {
478 lStatus = pdPASS;
479 }
480 else
481 {
482 lStatus = pdFAIL;
483 }
484 }
485
486 configASSERT( lStatus == pdPASS );
487
488 return lStatus;
489 }
490 /*-----------------------------------------------------------*/
491
