1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29
30 #ifndef PORTMACRO_H
31 #define PORTMACRO_H
32
33
34 /* *INDENT-OFF* */
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 /* *INDENT-ON* */
39
40 /*-----------------------------------------------------------
41 * Port specific definitions.
42 *
43 * The settings in this file configure FreeRTOS correctly for the
44 * given hardware and compiler.
45 *
46 * These settings should not be altered.
47 *-----------------------------------------------------------
48 */
49
50 /* Type definitions. */
51 #define portCHAR char
52 #define portFLOAT float
53 #define portDOUBLE double
54 #define portLONG long
55 #define portSHORT short
56 #define portSTACK_TYPE uint32_t
57 #define portBASE_TYPE long
58
59 typedef portSTACK_TYPE StackType_t;
60 typedef long BaseType_t;
61 typedef unsigned long UBaseType_t;
62
63 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
64 typedef uint16_t TickType_t;
65 #define portMAX_DELAY ( TickType_t ) 0xffff
66 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
67 typedef uint32_t TickType_t;
68 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
69
70 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
71 * not need to be guarded with a critical section. */
72 #define portTICK_TYPE_IS_ATOMIC 1
73 #else
74 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
75 #endif
76
77 /*-----------------------------------------------------------*/
78
79 /* MPU specific constants. */
80 #define portUSING_MPU_WRAPPERS 1
81 #define portPRIVILEGE_BIT ( 0x80000000UL )
82
83 #define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
84 #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
85 #define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
86 #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
87 #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
88 #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
89 #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
90
91 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
92 * Register (RASR). */
93 #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
94 #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
95
96 /* MPU settings that can be overriden in FreeRTOSConfig.h. */
97 #ifndef configTOTAL_MPU_REGIONS
98 /* Define to 8 for backward compatibility. */
99 #define configTOTAL_MPU_REGIONS ( 8UL )
100 #endif
101
102 /*
103 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
104 * memory type, and where necessary the cacheable and shareable properties
105 * of the memory region.
106 *
107 * The TEX, C, and B bits together indicate the memory type of the region,
108 * and:
109 * - For Normal memory, the cacheable properties of the region.
110 * - For Device memory, whether the region is shareable.
111 *
112 * For Normal memory regions, the S bit indicates whether the region is
113 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
114 *
115 * See the following two tables for setting TEX, S, C and B bits for
116 * unprivileged flash, privileged flash and privileged RAM regions.
117 *
118 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
119 | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
120 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
121 | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
122 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
123 | 000 | 0 | 1 | Device | Shared device | Shareable |
124 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
125 | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
126 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
127 | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
128 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
129 | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
130 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
131 | 001 | 0 | 1 | Reserved | Reserved | Reserved |
132 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
133 | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
134 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
135 | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
136 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
137 | 010 | 0 | 0 | Device | Non-shared device | Not shareable |
138 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
139 | 010 | 0 | 1 | Reserved | Reserved | Reserved |
140 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
141 | 010 | 1 | X | Reserved | Reserved | Reserved |
142 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
143 | 011 | X | X | Reserved | Reserved | Reserved |
144 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
145 | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
146 | | | | | outer cacheability rules that must be exported on the | |
147 | | | | | bus. See the table below for the cacheability policy | |
148 | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
149 +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
150 |
151 +-----------------------------------------+----------------------------------------+
152 | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
153 +-----------------------------------------+----------------------------------------+
154 | 00 | Non-cacheable |
155 +-----------------------------------------+----------------------------------------+
156 | 01 | Write-back, write and read allocate |
157 +-----------------------------------------+----------------------------------------+
158 | 10 | Write-through, no write allocate |
159 +-----------------------------------------+----------------------------------------+
160 | 11 | Write-back, no write allocate |
161 +-----------------------------------------+----------------------------------------+
162 */
163
164 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
165 * region. */
166 #ifndef configTEX_S_C_B_FLASH
167 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
168 #define configTEX_S_C_B_FLASH ( 0x07UL )
169 #endif
170
171 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
172 * region. */
173 #ifndef configTEX_S_C_B_SRAM
174 /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
175 #define configTEX_S_C_B_SRAM ( 0x07UL )
176 #endif
177
178 #define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
179 #define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
180 #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
181 #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
182 #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
183 #define portFIRST_CONFIGURABLE_REGION ( 0UL )
184 #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
185 #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
186 #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
187
188 #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
189
190 typedef struct MPU_REGION_REGISTERS
191 {
192 uint32_t ulRegionBaseAddress;
193 uint32_t ulRegionAttribute;
194 } xMPU_REGION_REGISTERS;
195
196 typedef struct MPU_REGION_SETTINGS
197 {
198 uint32_t ulRegionStartAddress;
199 uint32_t ulRegionEndAddress;
200 uint32_t ulRegionPermissions;
201 } xMPU_REGION_SETTINGS;
202
203 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
204
205 #ifndef configSYSTEM_CALL_STACK_SIZE
206 #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2.
207 #endif
208
209 typedef struct SYSTEM_CALL_STACK_INFO
210 {
211 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ];
212 uint32_t * pulSystemCallStack;
213 uint32_t * pulTaskStack;
214 uint32_t ulLinkRegisterAtSystemCallEntry;
215 } xSYSTEM_CALL_STACK_INFO;
216
217 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */
218
219 #define MAX_CONTEXT_SIZE ( 52 )
220
221 /* Size of an Access Control List (ACL) entry in bits. */
222 #define portACL_ENTRY_SIZE_BITS ( 32U )
223
224 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
225 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
226 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
227
228 typedef struct MPU_SETTINGS
229 {
230 xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
231 xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ];
232 uint32_t ulContext[ MAX_CONTEXT_SIZE ];
233 uint32_t ulTaskFlags;
234
235 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
236 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
237 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
238 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
239 #endif
240 #endif
241 } xMPU_SETTINGS;
242
243 /* Architecture specifics. */
244 #define portSTACK_GROWTH ( -1 )
245 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
246 #define portBYTE_ALIGNMENT 8
247 #define portDONT_DISCARD __attribute__( ( used ) )
248 /*-----------------------------------------------------------*/
249
250 /* SVC numbers for various services. */
251 #define portSVC_START_SCHEDULER 100
252 #define portSVC_YIELD 101
253 #define portSVC_RAISE_PRIVILEGE 102
254 #define portSVC_SYSTEM_CALL_EXIT 103
255
256 /* Scheduler utilities. */
257
258 #define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
259 #define portYIELD_WITHIN_API() \
260 { \
261 /* Set a PendSV to request a context switch. */ \
262 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
263 \
264 /* Barriers are normally not required but do ensure the code is completely \
265 * within the specified behaviour for the architecture. */ \
266 __asm volatile ( "dsb" ::: "memory" ); \
267 __asm volatile ( "isb" ); \
268 }
269
270 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
271 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
272 #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
273 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
274 /*-----------------------------------------------------------*/
275
276 /* Critical section management. */
277 extern void vPortEnterCritical( void );
278 extern void vPortExitCritical( void );
279 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
280 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
281 #define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
282 #define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
283 #define portENTER_CRITICAL() vPortEnterCritical()
284 #define portEXIT_CRITICAL() vPortExitCritical()
285
286 /*-----------------------------------------------------------*/
287
288 /* Task function macros as described on the FreeRTOS.org WEB site. These are
289 * not necessary for to use this port. They are defined so the common demo files
290 * (which build with all the ports) will build. */
291 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
292 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
293 /*-----------------------------------------------------------*/
294
295 /* Architecture specific optimisations. */
296 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
297 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
298 #endif
299
300 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
301
302 /* Generic helper function. */
ucPortCountLeadingZeros(uint32_t ulBitmap)303 __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
304 {
305 uint8_t ucReturn;
306
307 __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
308
309 return ucReturn;
310 }
311
312 /* Check the configuration. */
313 #if ( configMAX_PRIORITIES > 32 )
314 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
315 #endif
316
317 /* Store/clear the ready priorities in a bit map. */
318 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
319 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
320
321 /*-----------------------------------------------------------*/
322
323 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
324
325 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
326
327 /*-----------------------------------------------------------*/
328
329 #ifdef configASSERT
330 void vPortValidateInterruptPriority( void );
331 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
332 #endif
333
334 /* portNOP() is not required by this port. */
335 #define portNOP()
336
337 #define portINLINE __inline
338
339 #ifndef portFORCE_INLINE
340 #define portFORCE_INLINE inline __attribute__( ( always_inline ) )
341 #endif
342 /*-----------------------------------------------------------*/
343
344 extern BaseType_t xIsPrivileged( void );
345 extern void vResetPrivilege( void );
346
347 /**
348 * @brief Checks whether or not the processor is privileged.
349 *
350 * @return 1 if the processor is already privileged, 0 otherwise.
351 */
352 #define portIS_PRIVILEGED() xIsPrivileged()
353
354 /**
355 * @brief Raise an SVC request to raise privilege.
356 */
357 #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
358
359 /**
360 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
361 * register.
362 */
363 #define portRESET_PRIVILEGE() vResetPrivilege()
364 /*-----------------------------------------------------------*/
365
366 extern BaseType_t xPortIsTaskPrivileged( void );
367
368 /**
369 * @brief Checks whether or not the calling task is privileged.
370 *
371 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
372 */
373 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
374 /*-----------------------------------------------------------*/
375
xPortIsInsideInterrupt(void)376 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
377 {
378 uint32_t ulCurrentInterrupt;
379 BaseType_t xReturn;
380
381 /* Obtain the number of the currently executing interrupt. */
382 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
383
384 if( ulCurrentInterrupt == 0 )
385 {
386 xReturn = pdFALSE;
387 }
388 else
389 {
390 xReturn = pdTRUE;
391 }
392
393 return xReturn;
394 }
395
396 /*-----------------------------------------------------------*/
397
vPortRaiseBASEPRI(void)398 portFORCE_INLINE static void vPortRaiseBASEPRI( void )
399 {
400 uint32_t ulNewBASEPRI;
401
402 __asm volatile
403 (
404 " mov %0, %1 \n"
405 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
406 " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
407 #endif
408 " msr basepri, %0 \n"
409 " isb \n"
410 " dsb \n"
411 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
412 " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
413 #endif
414 : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
415 );
416 }
417
418 /*-----------------------------------------------------------*/
419
ulPortRaiseBASEPRI(void)420 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
421 {
422 uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
423
424 __asm volatile
425 (
426 " mrs %0, basepri \n"
427 " mov %1, %2 \n"
428 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
429 " cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
430 #endif
431 " msr basepri, %1 \n"
432 " isb \n"
433 " dsb \n"
434 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
435 " cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
436 #endif
437 : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
438 );
439
440 /* This return will not be reached but is necessary to prevent compiler
441 * warnings. */
442 return ulOriginalBASEPRI;
443 }
444 /*-----------------------------------------------------------*/
445
vPortSetBASEPRI(uint32_t ulNewMaskValue)446 portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
447 {
448 __asm volatile
449 (
450 " msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
451 );
452 }
453 /*-----------------------------------------------------------*/
454
455 #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
456
457 #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
458 #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
459 #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
460 #endif
461 /*-----------------------------------------------------------*/
462
463 /* *INDENT-OFF* */
464 #ifdef __cplusplus
465 }
466 #endif
467 /* *INDENT-ON* */
468
469 #endif /* PORTMACRO_H */
470
