1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4 MPU port.
31 *----------------------------------------------------------*/
32
33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
34 * all the API functions to use the MPU wrappers. That should only be done when
35 * task.h is included from an application file. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Scheduler includes. */
39 #include "FreeRTOS.h"
40 #include "task.h"
41 #include "mpu_syscall_numbers.h"
42
43 #ifndef __VFP_FP__
44 #error This port can only be used when the project options are configured to enable hardware floating point support.
45 #endif
46
47 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
48
49 #ifndef configSYSTICK_CLOCK_HZ
50 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
51 /* Ensure the SysTick is clocked at the same frequency as the core. */
52 #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
53 #else
54
55 /* The way the SysTick is clocked is not modified in case it is not the same
56 * as the core. */
57 #define portNVIC_SYSTICK_CLK ( 0 )
58 #endif
59
60 #ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS
61 #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security."
62 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1
63 #endif
64
65 /* Constants required to access and manipulate the NVIC. */
66 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
67 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
68 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
69 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
70 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
71 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
72 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
73
74 /* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure
75 * that a work around is active for errata 837070. */
76 #define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
77 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
78 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
79
80 /* Constants required to access and manipulate the MPU. */
81 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
82 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
83 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
84 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
85 #define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
86 #define portMPU_ENABLE ( 0x01UL )
87 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
88 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
89 #define portMPU_REGION_VALID ( 0x10UL )
90 #define portMPU_REGION_ENABLE ( 0x01UL )
91 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
92 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
93
94 /* Constants required to access and manipulate the SysTick. */
95 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
96 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
97 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
98 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
99 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
100 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
101
102 /* Constants required to manipulate the VFP. */
103 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
104 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
105
106 /* Constants required to set up the initial stack. */
107 #define portINITIAL_XPSR ( 0x01000000UL )
108 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
109 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
110 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
111
112 /* Constants required to check the validity of an interrupt priority. */
113 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
114 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
115 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
116 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
117 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
118 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
119 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
120 #define portPRIGROUP_SHIFT ( 8UL )
121
122 /* Constants used during system call enter and exit. */
123 #define portPSR_STACK_PADDING_MASK ( 1UL << 9UL )
124 #define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL )
125
126 /* Offsets in the stack to the parameters when inside the SVC handler. */
127 #define portOFFSET_TO_LR ( 5 )
128 #define portOFFSET_TO_PC ( 6 )
129 #define portOFFSET_TO_PSR ( 7 )
130
131
132 /* For strict compliance with the Cortex-M spec the task start address should
133 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
134 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
135
136 /* Does addr lie within [start, end] address range? */
137 #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
138 ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
139
140 /* Is the access request satisfied by the available permissions? */
141 #define portIS_AUTHORIZED( accessRequest, permissions ) \
142 ( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
143
144 /* Max value that fits in a uint32_t type. */
145 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
146
147 /* Check if adding a and b will result in overflow. */
148 #define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) )
149 /*-----------------------------------------------------------*/
150
151 /*
152 * Configure a number of standard MPU regions that are used by all tasks.
153 */
154 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
155
156 /*
157 * Return the smallest MPU region size that a given number of bytes will fit
158 * into. The region size is returned as the value that should be programmed
159 * into the region attribute register for that region.
160 */
161 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
162
163 /*
164 * Setup the timer to generate the tick interrupts. The implementation in this
165 * file is weak to allow application writers to change the timer used to
166 * generate the tick interrupt.
167 */
168 void vPortSetupTimerInterrupt( void );
169
170 /*
171 * Standard FreeRTOS exception handlers.
172 */
173 void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
174 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
175 void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
176
177 /*
178 * Starts the scheduler by restoring the context of the first task to run.
179 */
180 static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
181
182 /*
183 * C portion of the SVC handler. The SVC handler is split between an asm entry
184 * and a C wrapper for simplicity of coding and maintenance.
185 */
186 void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
187
188 /*
189 * Function to enable the VFP.
190 */
191 static void vPortEnableVFP( void ) __attribute__( ( naked ) );
192
193 /**
194 * @brief Checks whether or not the processor is privileged.
195 *
196 * @return 1 if the processor is already privileged, 0 otherwise.
197 */
198 BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
199
200 /**
201 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
202 * register.
203 *
204 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
205 * Bit[0] = 0 --> The processor is running privileged
206 * Bit[0] = 1 --> The processor is running unprivileged.
207 */
208 void vResetPrivilege( void ) __attribute__( ( naked ) );
209
210 /**
211 * @brief Enter critical section.
212 */
213 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
214 void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
215 #else
216 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
217 #endif
218
219 /**
220 * @brief Exit from critical section.
221 */
222 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
223 void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
224 #else
225 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
226 #endif
227
228 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
229
230 /**
231 * @brief Sets up the system call stack so that upon returning from
232 * SVC, the system call stack is used.
233 *
234 * @param pulTaskStack The current SP when the SVC was raised.
235 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
236 * @param ucSystemCallNumber The system call number of the system call.
237 */
238 void vSystemCallEnter( uint32_t * pulTaskStack,
239 uint32_t ulLR,
240 uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION;
241
242 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
243
244 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
245
246 /**
247 * @brief Raise SVC for exiting from a system call.
248 */
249 void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
250
251 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
252
253 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
254
255 /**
256 * @brief Sets up the task stack so that upon returning from
257 * SVC, the task stack is used again.
258 *
259 * @param pulSystemCallStack The current SP when the SVC was raised.
260 * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler.
261 */
262 void vSystemCallExit( uint32_t * pulSystemCallStack,
263 uint32_t ulLR ) PRIVILEGED_FUNCTION;
264
265 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
266
267 /**
268 * @brief Checks whether or not the calling task is privileged.
269 *
270 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
271 */
272 BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION;
273 /*-----------------------------------------------------------*/
274
275 /* Each task maintains its own interrupt status in the critical nesting
276 * variable. Note this is not saved as part of the task context as context
277 * switches can only occur when uxCriticalNesting is zero. */
278 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
279
280 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
281
282 /*
283 * This variable is set to pdTRUE when the scheduler is started.
284 */
285 PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE;
286
287 #endif
288
289 /*
290 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
291 * FreeRTOS API functions are not called from interrupts that have been assigned
292 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
293 */
294 #if ( configASSERT_DEFINED == 1 )
295 static uint8_t ucMaxSysCallPriority = 0;
296 static uint32_t ulMaxPRIGROUPValue = 0;
297 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
298 #endif /* configASSERT_DEFINED */
299
300 /*-----------------------------------------------------------*/
301
302 /*
303 * See header file for description.
304 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters,BaseType_t xRunPrivileged,xMPU_SETTINGS * xMPUSettings)305 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
306 TaskFunction_t pxCode,
307 void * pvParameters,
308 BaseType_t xRunPrivileged,
309 xMPU_SETTINGS * xMPUSettings )
310 {
311 if( xRunPrivileged == pdTRUE )
312 {
313 xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
314 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED;
315 }
316 else
317 {
318 xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
319 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED;
320 }
321 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */
322 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */
323 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */
324 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */
325 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */
326 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */
327 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */
328 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */
329 xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */
330
331 xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */
332 xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */
333 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */
334 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */
335 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */
336 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */
337 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */
338 xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */
339 xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */
340
341 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
342 {
343 /* Ensure that the system call stack is double word aligned. */
344 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] );
345 xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) &
346 ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) );
347
348 /* This is not NULL only for the duration of a system call. */
349 xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL;
350 }
351 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
352
353 return &( xMPUSettings->ulContext[ 19 ] );
354 }
355 /*-----------------------------------------------------------*/
356
357 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
358
vPortSVCHandler(void)359 void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
360 {
361 __asm volatile
362 (
363 ".syntax unified \n"
364 ".extern vSVCHandler_C \n"
365 ".extern vSystemCallEnter \n"
366 ".extern vSystemCallExit \n"
367 " \n"
368 "tst lr, #4 \n"
369 "ite eq \n"
370 "mrseq r0, msp \n"
371 "mrsne r0, psp \n"
372 " \n"
373 "ldr r1, [r0, #24] \n"
374 "ldrb r2, [r1, #-2] \n"
375 "cmp r2, %0 \n"
376 "blt syscall_enter \n"
377 "cmp r2, %1 \n"
378 "beq syscall_exit \n"
379 "b vSVCHandler_C \n"
380 " \n"
381 "syscall_enter: \n"
382 " mov r1, lr \n"
383 " b vSystemCallEnter \n"
384 " \n"
385 "syscall_exit: \n"
386 " mov r1, lr \n"
387 " b vSystemCallExit \n"
388 " \n"
389 : /* No outputs. */
390 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
391 : "r0", "r1", "r2", "memory"
392 );
393 }
394
395 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
396
vPortSVCHandler(void)397 void vPortSVCHandler( void )
398 {
399 /* Assumes psp was in use. */
400 __asm volatile
401 (
402 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
403 " tst lr, #4 \n"
404 " ite eq \n"
405 " mrseq r0, msp \n"
406 " mrsne r0, psp \n"
407 #else
408 " mrs r0, psp \n"
409 #endif
410 " b %0 \n"
411 ::"i" ( vSVCHandler_C ) : "r0", "memory"
412 );
413 }
414
415 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
416 /*-----------------------------------------------------------*/
417
vSVCHandler_C(uint32_t * pulParam)418 void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */
419 {
420 uint8_t ucSVCNumber;
421 uint32_t ulPC;
422
423 #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) )
424 #if defined( __ARMCC_VERSION )
425 /* Declaration when these variable are defined in code instead of being
426 * exported from linker scripts. */
427 extern uint32_t * __syscalls_flash_start__;
428 extern uint32_t * __syscalls_flash_end__;
429 #else
430 /* Declaration when these variable are exported from linker scripts. */
431 extern uint32_t __syscalls_flash_start__[];
432 extern uint32_t __syscalls_flash_end__[];
433 #endif /* #if defined( __ARMCC_VERSION ) */
434 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */
435
436 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
437 * argument (r0) is pulParam[ 0 ]. */
438 ulPC = pulParam[ portOFFSET_TO_PC ];
439 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
440
441 switch( ucSVCNumber )
442 {
443 case portSVC_START_SCHEDULER:
444 portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
445 prvRestoreContextOfFirstTask();
446 break;
447
448 case portSVC_YIELD:
449 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
450
451 /* Barriers are normally not required
452 * but do ensure the code is completely
453 * within the specified behaviour for the
454 * architecture. */
455 __asm volatile ( "dsb" ::: "memory" );
456 __asm volatile ( "isb" );
457
458 break;
459
460 #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
461 #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
462 case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
463 * svc was raised from any of the
464 * system calls. */
465
466 if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
467 ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
468 {
469 __asm volatile
470 (
471 " mrs r1, control \n" /* Obtain current control value. */
472 " bic r1, #1 \n" /* Set privilege bit. */
473 " msr control, r1 \n" /* Write back new control value. */
474 ::: "r1", "memory"
475 );
476 }
477
478 break;
479 #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
480 case portSVC_RAISE_PRIVILEGE:
481 __asm volatile
482 (
483 " mrs r1, control \n" /* Obtain current control value. */
484 " bic r1, #1 \n" /* Set privilege bit. */
485 " msr control, r1 \n" /* Write back new control value. */
486 ::: "r1", "memory"
487 );
488 break;
489 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
490 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
491
492 default: /* Unknown SVC call. */
493 break;
494 }
495 }
496 /*-----------------------------------------------------------*/
497
498 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
499
vSystemCallEnter(uint32_t * pulTaskStack,uint32_t ulLR,uint8_t ucSystemCallNumber)500 void vSystemCallEnter( uint32_t * pulTaskStack,
501 uint32_t ulLR,
502 uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */
503 {
504 extern TaskHandle_t pxCurrentTCB;
505 extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ];
506 xMPU_SETTINGS * pxMpuSettings;
507 uint32_t * pulSystemCallStack;
508 uint32_t ulStackFrameSize, ulSystemCallLocation, i;
509
510 #if defined( __ARMCC_VERSION )
511 /* Declaration when these variable are defined in code instead of being
512 * exported from linker scripts. */
513 extern uint32_t * __syscalls_flash_start__;
514 extern uint32_t * __syscalls_flash_end__;
515 #else
516 /* Declaration when these variable are exported from linker scripts. */
517 extern uint32_t __syscalls_flash_start__[];
518 extern uint32_t __syscalls_flash_end__[];
519 #endif /* #if defined( __ARMCC_VERSION ) */
520
521 ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ];
522 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
523
524 /* Checks:
525 * 1. SVC is raised from the system call section (i.e. application is
526 * not raising SVC directly).
527 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as
528 * it is non-NULL only during the execution of a system call (i.e.
529 * between system call enter and exit).
530 * 3. System call is not for a kernel API disabled by the configuration
531 * in FreeRTOSConfig.h.
532 * 4. We do not need to check that ucSystemCallNumber is within range
533 * because the assembly SVC handler checks that before calling
534 * this function.
535 */
536 if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) &&
537 ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) &&
538 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) &&
539 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) )
540 {
541 pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack;
542
543 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
544 {
545 /* Extended frame i.e. FPU in use. */
546 ulStackFrameSize = 26;
547 __asm volatile
548 (
549 " vpush {s0} \n" /* Trigger lazy stacking. */
550 " vpop {s0} \n" /* Nullify the affect of the above instruction. */
551 ::: "memory"
552 );
553 }
554 else
555 {
556 /* Standard frame i.e. FPU not in use. */
557 ulStackFrameSize = 8;
558 }
559
560 /* Make space on the system call stack for the stack frame. */
561 pulSystemCallStack = pulSystemCallStack - ulStackFrameSize;
562
563 /* Copy the stack frame. */
564 for( i = 0; i < ulStackFrameSize; i++ )
565 {
566 pulSystemCallStack[ i ] = pulTaskStack[ i ];
567 }
568
569 /* Use the pulSystemCallStack in thread mode. */
570 __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) );
571
572 /* Raise the privilege for the duration of the system call. */
573 __asm volatile
574 (
575 " mrs r1, control \n" /* Obtain current control value. */
576 " bic r1, #1 \n" /* Clear nPRIV bit. */
577 " msr control, r1 \n" /* Write back new control value. */
578 ::: "r1", "memory"
579 );
580
581 /* Remember the location where we should copy the stack frame when we exit from
582 * the system call. */
583 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulStackFrameSize;
584
585 /* Store the value of the Link Register before the SVC was raised.
586 * It contains the address of the caller of the System Call entry
587 * point (i.e. the caller of the MPU_<API>). We need to restore it
588 * when we exit from the system call. */
589 pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ];
590
591 /* Start executing the system call upon returning from this handler. */
592 pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ];
593
594 /* Raise a request to exit from the system call upon finishing the
595 * system call. */
596 pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit;
597
598 /* Record if the hardware used padding to force the stack pointer
599 * to be double word aligned. */
600 if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK )
601 {
602 pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG;
603 }
604 else
605 {
606 pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG );
607 }
608
609 /* We ensure in pxPortInitialiseStack that the system call stack is
610 * double word aligned and therefore, there is no need of padding.
611 * Clear the bit[9] of stacked xPSR. */
612 pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
613 }
614 }
615
616 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
617 /*-----------------------------------------------------------*/
618
619 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
620
vRequestSystemCallExit(void)621 void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */
622 {
623 __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" );
624 }
625
626 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
627 /*-----------------------------------------------------------*/
628
629 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
630
vSystemCallExit(uint32_t * pulSystemCallStack,uint32_t ulLR)631 void vSystemCallExit( uint32_t * pulSystemCallStack,
632 uint32_t ulLR ) /* PRIVILEGED_FUNCTION */
633 {
634 extern TaskHandle_t pxCurrentTCB;
635 xMPU_SETTINGS * pxMpuSettings;
636 uint32_t * pulTaskStack;
637 uint32_t ulStackFrameSize, ulSystemCallLocation, i;
638
639 #if defined( __ARMCC_VERSION )
640 /* Declaration when these variable are defined in code instead of being
641 * exported from linker scripts. */
642 extern uint32_t * __privileged_functions_start__;
643 extern uint32_t * __privileged_functions_end__;
644 #else
645 /* Declaration when these variable are exported from linker scripts. */
646 extern uint32_t __privileged_functions_start__[];
647 extern uint32_t __privileged_functions_end__[];
648 #endif /* #if defined( __ARMCC_VERSION ) */
649
650 ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ];
651 pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB );
652
653 /* Checks:
654 * 1. SVC is raised from the privileged code (i.e. application is not
655 * raising SVC directly). This SVC is only raised from
656 * vRequestSystemCallExit which is in the privileged code section.
657 * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL -
658 * this means that we previously entered a system call and the
659 * application is not attempting to exit without entering a system
660 * call.
661 */
662 if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) &&
663 ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) &&
664 ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) )
665 {
666 pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack;
667
668 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL )
669 {
670 /* Extended frame i.e. FPU in use. */
671 ulStackFrameSize = 26;
672 __asm volatile
673 (
674 " vpush {s0} \n" /* Trigger lazy stacking. */
675 " vpop {s0} \n" /* Nullify the affect of the above instruction. */
676 ::: "memory"
677 );
678 }
679 else
680 {
681 /* Standard frame i.e. FPU not in use. */
682 ulStackFrameSize = 8;
683 }
684
685 /* Make space on the task stack for the stack frame. */
686 pulTaskStack = pulTaskStack - ulStackFrameSize;
687
688 /* Copy the stack frame. */
689 for( i = 0; i < ulStackFrameSize; i++ )
690 {
691 pulTaskStack[ i ] = pulSystemCallStack[ i ];
692 }
693
694 /* Use the pulTaskStack in thread mode. */
695 __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) );
696
697 /* Drop the privilege before returning to the thread mode. */
698 __asm volatile
699 (
700 " mrs r1, control \n" /* Obtain current control value. */
701 " orr r1, #1 \n" /* Set nPRIV bit. */
702 " msr control, r1 \n" /* Write back new control value. */
703 ::: "r1", "memory"
704 );
705
706 /* Return to the caller of the System Call entry point (i.e. the
707 * caller of the MPU_<API>). */
708 pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
709 /* Ensure that LR has a valid value.*/
710 pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry;
711
712 /* If the hardware used padding to force the stack pointer
713 * to be double word aligned, set the stacked xPSR bit[9],
714 * otherwise clear it. */
715 if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG )
716 {
717 pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK;
718 }
719 else
720 {
721 pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK );
722 }
723
724 /* This is not NULL only for the duration of the system call. */
725 pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL;
726 }
727 }
728
729 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
730 /*-----------------------------------------------------------*/
731
xPortIsTaskPrivileged(void)732 BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */
733 {
734 BaseType_t xTaskIsPrivileged = pdFALSE;
735 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
736
737 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
738 {
739 xTaskIsPrivileged = pdTRUE;
740 }
741
742 return xTaskIsPrivileged;
743 }
744 /*-----------------------------------------------------------*/
745
prvRestoreContextOfFirstTask(void)746 static void prvRestoreContextOfFirstTask( void )
747 {
748 __asm volatile
749 (
750 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
751 " ldr r0, [r0] \n"
752 " ldr r0, [r0] \n"
753 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
754 " \n"
755 /*------------ Program MPU. ------------ */
756 " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
757 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
758 " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
759 " \n"
760 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
761 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
762 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
763 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
764 " str r3, [r0] \n" /* Disable MPU. */
765 " \n"
766 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
767 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
768 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
769 " \n"
770 #if ( configTOTAL_MPU_REGIONS == 16 )
771 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
772 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
773 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
774 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
775 #endif /* configTOTAL_MPU_REGIONS == 16. */
776 " \n"
777 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
778 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
779 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
780 " str r3, [r0] \n" /* Enable MPU. */
781 " dsb \n" /* Force memory writes before continuing. */
782 " \n"
783 /*---------- Restore Context. ---------- */
784 " ldr r3, pxCurrentTCBConst2 \n" /* r3 = pxCurrentTCBConst2. */
785 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
786 " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
787 " \n"
788 " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
789 " msr psp, r0 \n"
790 " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
791 " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */
792 " msr control, r3 \n"
793 " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */
794 " \n"
795 " mov r0, #0 \n"
796 " msr basepri, r0 \n"
797 " bx lr \n"
798 " \n"
799 " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */
800 " .align 4 \n"
801 " pxCurrentTCBConst2: .word pxCurrentTCB\n"
802 );
803 }
804 /*-----------------------------------------------------------*/
805
806 /*
807 * See header file for description.
808 */
xPortStartScheduler(void)809 BaseType_t xPortStartScheduler( void )
810 {
811 /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0
812 * and r0p1 cores. */
813 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
814 configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
815 #else
816 /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
817 * configENABLE_ERRATA_837070_WORKAROUND to 1 in your
818 * FreeRTOSConfig.h. */
819 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
820 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
821 #endif
822
823 #if ( configASSERT_DEFINED == 1 )
824 {
825 volatile uint8_t ucOriginalPriority;
826 volatile uint32_t ulImplementedPrioBits = 0;
827 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
828 volatile uint8_t ucMaxPriorityValue;
829
830 /* Determine the maximum priority from which ISR safe FreeRTOS API
831 * functions can be called. ISR safe functions are those that end in
832 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
833 * ensure interrupt entry is as fast and simple as possible.
834 *
835 * Save the interrupt priority value that is about to be clobbered. */
836 ucOriginalPriority = *pucFirstUserPriorityRegister;
837
838 /* Determine the number of priority bits available. First write to all
839 * possible bits. */
840 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
841
842 /* Read the value back to see how many bits stuck. */
843 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
844
845 /* Use the same mask on the maximum system call priority. */
846 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
847
848 /* Check that the maximum system call priority is nonzero after
849 * accounting for the number of priority bits supported by the
850 * hardware. A priority of 0 is invalid because setting the BASEPRI
851 * register to 0 unmasks all interrupts, and interrupts with priority 0
852 * cannot be masked using BASEPRI.
853 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
854 configASSERT( ucMaxSysCallPriority );
855
856 /* Check that the bits not implemented in hardware are zero in
857 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
858 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
859
860 /* Calculate the maximum acceptable priority group value for the number
861 * of bits read back. */
862
863 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
864 {
865 ulImplementedPrioBits++;
866 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
867 }
868
869 if( ulImplementedPrioBits == 8 )
870 {
871 /* When the hardware implements 8 priority bits, there is no way for
872 * the software to configure PRIGROUP to not have sub-priorities. As
873 * a result, the least significant bit is always used for sub-priority
874 * and there are 128 preemption priorities and 2 sub-priorities.
875 *
876 * This may cause some confusion in some cases - for example, if
877 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
878 * priority interrupts will be masked in Critical Sections as those
879 * are at the same preemption priority. This may appear confusing as
880 * 4 is higher (numerically lower) priority than
881 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
882 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
883 * to 4, this confusion does not happen and the behaviour remains the same.
884 *
885 * The following assert ensures that the sub-priority bit in the
886 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
887 * confusion. */
888 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
889 ulMaxPRIGROUPValue = 0;
890 }
891 else
892 {
893 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
894 }
895
896 /* Shift the priority group value back to its position within the AIRCR
897 * register. */
898 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
899 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
900
901 /* Restore the clobbered interrupt priority register to its original
902 * value. */
903 *pucFirstUserPriorityRegister = ucOriginalPriority;
904 }
905 #endif /* configASSERT_DEFINED */
906
907 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
908 * handler higher priority so it can be used to exit a critical section (where
909 * lower priorities are masked). */
910 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
911 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
912
913 /* Configure the regions in the MPU that are common to all tasks. */
914 prvSetupMPU();
915
916 /* Start the timer that generates the tick ISR. Interrupts are disabled
917 * here already. */
918 vPortSetupTimerInterrupt();
919
920 /* Initialise the critical nesting count ready for the first task. */
921 uxCriticalNesting = 0;
922
923 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
924 {
925 xSchedulerRunning = pdTRUE;
926 }
927 #endif
928
929 /* Ensure the VFP is enabled - it should be anyway. */
930 vPortEnableVFP();
931
932 /* Lazy save always. */
933 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
934
935 /* Start the first task. This also clears the bit that indicates the FPU is
936 * in use in case the FPU was used before the scheduler was started - which
937 * would otherwise result in the unnecessary leaving of space in the SVC stack
938 * for lazy saving of FPU registers. */
939 __asm volatile
940 (
941 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
942 " ldr r0, [r0] \n"
943 " ldr r0, [r0] \n"
944 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
945 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
946 " msr control, r0 \n"
947 " cpsie i \n" /* Globally enable interrupts. */
948 " cpsie f \n"
949 " dsb \n"
950 " isb \n"
951 " svc %0 \n" /* System call to start first task. */
952 " nop \n"
953 " .ltorg \n"
954 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
955 );
956
957 /* Should not get here! */
958 return 0;
959 }
960 /*-----------------------------------------------------------*/
961
vPortEndScheduler(void)962 void vPortEndScheduler( void )
963 {
964 /* Not implemented in ports where there is nothing to return to.
965 * Artificially force an assert. */
966 configASSERT( uxCriticalNesting == 1000UL );
967 }
968 /*-----------------------------------------------------------*/
969
vPortEnterCritical(void)970 void vPortEnterCritical( void )
971 {
972 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
973 if( portIS_PRIVILEGED() == pdFALSE )
974 {
975 portRAISE_PRIVILEGE();
976 portMEMORY_BARRIER();
977
978 portDISABLE_INTERRUPTS();
979 uxCriticalNesting++;
980 portMEMORY_BARRIER();
981
982 portRESET_PRIVILEGE();
983 portMEMORY_BARRIER();
984 }
985 else
986 {
987 portDISABLE_INTERRUPTS();
988 uxCriticalNesting++;
989 }
990 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
991 portDISABLE_INTERRUPTS();
992 uxCriticalNesting++;
993 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
994 }
995 /*-----------------------------------------------------------*/
996
vPortExitCritical(void)997 void vPortExitCritical( void )
998 {
999 #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
1000 if( portIS_PRIVILEGED() == pdFALSE )
1001 {
1002 portRAISE_PRIVILEGE();
1003 portMEMORY_BARRIER();
1004
1005 configASSERT( uxCriticalNesting );
1006 uxCriticalNesting--;
1007
1008 if( uxCriticalNesting == 0 )
1009 {
1010 portENABLE_INTERRUPTS();
1011 }
1012
1013 portMEMORY_BARRIER();
1014
1015 portRESET_PRIVILEGE();
1016 portMEMORY_BARRIER();
1017 }
1018 else
1019 {
1020 configASSERT( uxCriticalNesting );
1021 uxCriticalNesting--;
1022
1023 if( uxCriticalNesting == 0 )
1024 {
1025 portENABLE_INTERRUPTS();
1026 }
1027 }
1028 #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1029 configASSERT( uxCriticalNesting );
1030 uxCriticalNesting--;
1031
1032 if( uxCriticalNesting == 0 )
1033 {
1034 portENABLE_INTERRUPTS();
1035 }
1036 #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
1037 }
1038 /*-----------------------------------------------------------*/
1039
xPortPendSVHandler(void)1040 void xPortPendSVHandler( void )
1041 {
1042 /* This is a naked function. */
1043
1044 __asm volatile
1045 (
1046 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1047 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1048 " ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */
1049 " \n"
1050 /*------------ Save Context. ----------- */
1051 " mrs r3, control \n"
1052 " mrs r0, psp \n"
1053 " isb \n"
1054 " \n"
1055 " add r0, r0, #0x20 \n" /* Move r0 to location where s0 is saved. */
1056 " tst lr, #0x10 \n"
1057 " ittt eq \n"
1058 " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */
1059 " vldmiaeq r0, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
1060 " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
1061 " sub r0, r0, #0x20 \n" /* Set r0 back to the location of hardware saved context. */
1062 " \n"
1063 " stmia r1!, {r3-r11, lr} \n" /* Store CONTROL register, r4-r11 and LR. */
1064 " ldmia r0, {r4-r11} \n" /* Copy hardware saved context into r4-r11. */
1065 " stmia r1!, {r0, r4-r11} \n" /* Store original PSP (after hardware has saved context) and the hardware saved context. */
1066 " str r1, [r2] \n" /* Save the location from where the context should be restored as the first member of TCB. */
1067 " \n"
1068 /*---------- Select next task. --------- */
1069 " mov r0, %0 \n"
1070 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1071 " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1072 #endif
1073 " msr basepri, r0 \n"
1074 " dsb \n"
1075 " isb \n"
1076 #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
1077 " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
1078 #endif
1079 " bl vTaskSwitchContext \n"
1080 " mov r0, #0 \n"
1081 " msr basepri, r0 \n"
1082 " \n"
1083 /*------------ Program MPU. ------------ */
1084 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1085 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1086 " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */
1087 " \n"
1088 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
1089 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
1090 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
1091 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
1092 " str r3, [r0] \n" /* Disable MPU. */
1093 " \n"
1094 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */
1095 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
1096 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
1097 " \n"
1098 #if ( configTOTAL_MPU_REGIONS == 16 )
1099 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
1100 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
1101 " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
1102 " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
1103 #endif /* configTOTAL_MPU_REGIONS == 16. */
1104 " \n"
1105 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */
1106 " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */
1107 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
1108 " str r3, [r0] \n" /* Enable MPU. */
1109 " dsb \n" /* Force memory writes before continuing. */
1110 " \n"
1111 /*---------- Restore Context. ---------- */
1112 " ldr r3, pxCurrentTCBConst \n" /* r3 = pxCurrentTCBConst. */
1113 " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */
1114 " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */
1115 " \n"
1116 " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
1117 " msr psp, r0 \n"
1118 " stmia r0!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
1119 " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */
1120 " msr control, r3 \n"
1121
1122 " tst lr, #0x10 \n"
1123 " ittt eq \n"
1124 " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
1125 " vstmiaeq r0!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
1126 " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */
1127
1128 " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */
1129 " bx lr \n"
1130 " \n"
1131 " .ltorg \n" /* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */
1132 " .align 4 \n"
1133 " pxCurrentTCBConst: .word pxCurrentTCB \n"
1134 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
1135 );
1136 }
1137 /*-----------------------------------------------------------*/
1138
xPortSysTickHandler(void)1139 void xPortSysTickHandler( void )
1140 {
1141 uint32_t ulDummy;
1142
1143 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
1144 {
1145 /* Increment the RTOS tick. */
1146 if( xTaskIncrementTick() != pdFALSE )
1147 {
1148 /* Pend a context switch. */
1149 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
1150 }
1151 }
1152 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
1153 }
1154 /*-----------------------------------------------------------*/
1155
1156 /*
1157 * Setup the systick timer to generate the tick interrupts at the required
1158 * frequency.
1159 */
vPortSetupTimerInterrupt(void)1160 __attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
1161 {
1162 /* Stop and clear the SysTick. */
1163 portNVIC_SYSTICK_CTRL_REG = 0UL;
1164 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
1165
1166 /* Configure SysTick to interrupt at the requested rate. */
1167 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
1168 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
1169 }
1170 /*-----------------------------------------------------------*/
1171
1172 /* This is a naked function. */
vPortEnableVFP(void)1173 static void vPortEnableVFP( void )
1174 {
1175 __asm volatile
1176 (
1177 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
1178 " ldr r1, [r0] \n"
1179 " \n"
1180 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
1181 " str r1, [r0] \n"
1182 " bx r14 \n"
1183 " .ltorg \n"
1184 );
1185 }
1186 /*-----------------------------------------------------------*/
1187
prvSetupMPU(void)1188 static void prvSetupMPU( void )
1189 {
1190 #if defined( __ARMCC_VERSION )
1191 /* Declaration when these variable are defined in code instead of being
1192 * exported from linker scripts. */
1193 extern uint32_t * __privileged_functions_start__;
1194 extern uint32_t * __privileged_functions_end__;
1195 extern uint32_t * __FLASH_segment_start__;
1196 extern uint32_t * __FLASH_segment_end__;
1197 extern uint32_t * __privileged_data_start__;
1198 extern uint32_t * __privileged_data_end__;
1199 #else
1200 /* Declaration when these variable are exported from linker scripts. */
1201 extern uint32_t __privileged_functions_start__[];
1202 extern uint32_t __privileged_functions_end__[];
1203 extern uint32_t __FLASH_segment_start__[];
1204 extern uint32_t __FLASH_segment_end__[];
1205 extern uint32_t __privileged_data_start__[];
1206 extern uint32_t __privileged_data_end__[];
1207 #endif /* if defined( __ARMCC_VERSION ) */
1208
1209 /* The only permitted number of regions are 8 or 16. */
1210 configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
1211
1212 /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
1213 configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
1214
1215 /* Check the expected MPU is present. */
1216 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
1217 {
1218 /* First setup the unprivileged flash for unprivileged read only access. */
1219 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
1220 ( portMPU_REGION_VALID ) |
1221 ( portUNPRIVILEGED_FLASH_REGION );
1222
1223 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
1224 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1225 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
1226 ( portMPU_REGION_ENABLE );
1227
1228 /* Setup the privileged flash for privileged only access. This is where
1229 * the kernel code is placed. */
1230 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
1231 ( portMPU_REGION_VALID ) |
1232 ( portPRIVILEGED_FLASH_REGION );
1233
1234 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
1235 ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1236 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
1237 ( portMPU_REGION_ENABLE );
1238
1239 /* Setup the privileged data RAM region. This is where the kernel data
1240 * is placed. */
1241 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
1242 ( portMPU_REGION_VALID ) |
1243 ( portPRIVILEGED_RAM_REGION );
1244
1245 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
1246 ( portMPU_REGION_EXECUTE_NEVER ) |
1247 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1248 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
1249 ( portMPU_REGION_ENABLE );
1250
1251 /* By default allow everything to access the general peripherals. The
1252 * system peripherals and registers are protected. */
1253 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
1254 ( portMPU_REGION_VALID ) |
1255 ( portGENERAL_PERIPHERALS_REGION );
1256
1257 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
1258 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
1259 ( portMPU_REGION_ENABLE );
1260
1261 /* Enable the memory fault exception. */
1262 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
1263
1264 /* Enable the MPU with the background region configured. */
1265 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
1266 }
1267 }
1268 /*-----------------------------------------------------------*/
1269
prvGetMPURegionSizeSetting(uint32_t ulActualSizeInBytes)1270 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
1271 {
1272 uint32_t ulRegionSize, ulReturnValue = 4;
1273
1274 /* 32 is the smallest region size, 31 is the largest valid value for
1275 * ulReturnValue. */
1276 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
1277 {
1278 if( ulActualSizeInBytes <= ulRegionSize )
1279 {
1280 break;
1281 }
1282 else
1283 {
1284 ulReturnValue++;
1285 }
1286 }
1287
1288 /* Shift the code by one before returning so it can be written directly
1289 * into the the correct bit position of the attribute register. */
1290 return( ulReturnValue << 1UL );
1291 }
1292 /*-----------------------------------------------------------*/
1293
xIsPrivileged(void)1294 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
1295 {
1296 __asm volatile
1297 (
1298 " mrs r0, control \n" /* r0 = CONTROL. */
1299 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
1300 " ite ne \n"
1301 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
1302 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
1303 " bx lr \n" /* Return. */
1304 " \n"
1305 " .align 4 \n"
1306 ::: "r0", "memory"
1307 );
1308 }
1309 /*-----------------------------------------------------------*/
1310
vResetPrivilege(void)1311 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
1312 {
1313 __asm volatile
1314 (
1315 " mrs r0, control \n" /* r0 = CONTROL. */
1316 " orr r0, #1 \n" /* r0 = r0 | 1. */
1317 " msr control, r0 \n" /* CONTROL = r0. */
1318 " bx lr \n" /* Return to the caller. */
1319 ::: "r0", "memory"
1320 );
1321 }
1322 /*-----------------------------------------------------------*/
1323
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,uint32_t ulStackDepth)1324 void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
1325 const struct xMEMORY_REGION * const xRegions,
1326 StackType_t * pxBottomOfStack,
1327 uint32_t ulStackDepth )
1328 {
1329 #if defined( __ARMCC_VERSION )
1330 /* Declaration when these variable are defined in code instead of being
1331 * exported from linker scripts. */
1332 extern uint32_t * __SRAM_segment_start__;
1333 extern uint32_t * __SRAM_segment_end__;
1334 extern uint32_t * __privileged_data_start__;
1335 extern uint32_t * __privileged_data_end__;
1336 #else
1337 /* Declaration when these variable are exported from linker scripts. */
1338 extern uint32_t __SRAM_segment_start__[];
1339 extern uint32_t __SRAM_segment_end__[];
1340 extern uint32_t __privileged_data_start__[];
1341 extern uint32_t __privileged_data_end__[];
1342 #endif /* if defined( __ARMCC_VERSION ) */
1343
1344 int32_t lIndex;
1345 uint32_t ul;
1346
1347 if( xRegions == NULL )
1348 {
1349 /* No MPU regions are specified so allow access to all RAM. */
1350 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1351 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
1352 ( portMPU_REGION_VALID ) |
1353 ( portSTACK_REGION ); /* Region number. */
1354
1355 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1356 ( portMPU_REGION_READ_WRITE ) |
1357 ( portMPU_REGION_EXECUTE_NEVER ) |
1358 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1359 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
1360 ( portMPU_REGION_ENABLE );
1361
1362 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__;
1363 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__;
1364 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1365 tskMPU_WRITE_PERMISSION );
1366
1367 /* Invalidate user configurable regions. */
1368 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1369 {
1370 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1371 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1372 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1373 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1374 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1375 }
1376 }
1377 else
1378 {
1379 /* This function is called automatically when the task is created - in
1380 * which case the stack region parameters will be valid. At all other
1381 * times the stack parameters will not be valid and it is assumed that the
1382 * stack region has already been configured. */
1383 if( ulStackDepth > 0 )
1384 {
1385 /* Define the region that allows access to the stack. */
1386 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
1387 ( ( uint32_t ) pxBottomOfStack ) |
1388 ( portMPU_REGION_VALID ) |
1389 ( portSTACK_REGION ); /* Region number. */
1390
1391 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
1392 ( portMPU_REGION_READ_WRITE ) |
1393 ( portMPU_REGION_EXECUTE_NEVER ) |
1394 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
1395 ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
1396 ( portMPU_REGION_ENABLE );
1397
1398 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
1399 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) +
1400 ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL );
1401 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION |
1402 tskMPU_WRITE_PERMISSION );
1403 }
1404
1405 lIndex = 0;
1406
1407 for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
1408 {
1409 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
1410 {
1411 /* Translate the generic region definition contained in
1412 * xRegions into the CM4 specific MPU settings that are then
1413 * stored in xMPUSettings. */
1414 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
1415 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
1416 ( portMPU_REGION_VALID ) |
1417 ( ul - 1UL ); /* Region number. */
1418
1419 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
1420 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
1421 ( xRegions[ lIndex ].ulParameters ) |
1422 ( portMPU_REGION_ENABLE );
1423
1424 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress;
1425 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL );
1426 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1427
1428 if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) ||
1429 ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) )
1430 {
1431 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION;
1432 }
1433
1434 if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE )
1435 {
1436 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION );
1437 }
1438 }
1439 else
1440 {
1441 /* Invalidate the region. */
1442 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
1443 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
1444 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL;
1445 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL;
1446 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL;
1447 }
1448
1449 lIndex++;
1450 }
1451 }
1452 }
1453 /*-----------------------------------------------------------*/
1454
xPortIsAuthorizedToAccessBuffer(const void * pvBuffer,uint32_t ulBufferLength,uint32_t ulAccessRequested)1455 BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer,
1456 uint32_t ulBufferLength,
1457 uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */
1458
1459 {
1460 uint32_t i, ulBufferStartAddress, ulBufferEndAddress;
1461 BaseType_t xAccessGranted = pdFALSE;
1462 const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1463
1464 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1465 {
1466 xAccessGranted = pdTRUE;
1467 }
1468 else
1469 {
1470 if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE )
1471 {
1472 ulBufferStartAddress = ( uint32_t ) pvBuffer;
1473 ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL );
1474
1475 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ )
1476 {
1477 if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress,
1478 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1479 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1480 portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress,
1481 xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress,
1482 xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) &&
1483 portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) )
1484 {
1485 xAccessGranted = pdTRUE;
1486 break;
1487 }
1488 }
1489 }
1490 }
1491
1492 return xAccessGranted;
1493 }
1494 /*-----------------------------------------------------------*/
1495
1496 #if ( configASSERT_DEFINED == 1 )
1497
vPortValidateInterruptPriority(void)1498 void vPortValidateInterruptPriority( void )
1499 {
1500 uint32_t ulCurrentInterrupt;
1501 uint8_t ucCurrentPriority;
1502
1503 /* Obtain the number of the currently executing interrupt. */
1504 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
1505
1506 /* Is the interrupt number a user defined interrupt? */
1507 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
1508 {
1509 /* Look up the interrupt's priority. */
1510 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
1511
1512 /* The following assertion will fail if a service routine (ISR) for
1513 * an interrupt that has been assigned a priority above
1514 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
1515 * function. ISR safe FreeRTOS API functions must *only* be called
1516 * from interrupts that have been assigned a priority at or below
1517 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1518 *
1519 * Numerically low interrupt priority numbers represent logically high
1520 * interrupt priorities, therefore the priority of the interrupt must
1521 * be set to a value equal to or numerically *higher* than
1522 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
1523 *
1524 * Interrupts that use the FreeRTOS API must not be left at their
1525 * default priority of zero as that is the highest possible priority,
1526 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
1527 * and therefore also guaranteed to be invalid.
1528 *
1529 * FreeRTOS maintains separate thread and ISR API functions to ensure
1530 * interrupt entry is as fast and simple as possible.
1531 *
1532 * The following links provide detailed information:
1533 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
1534 * https://www.FreeRTOS.org/FAQHelp.html */
1535 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
1536 }
1537
1538 /* Priority grouping: The interrupt controller (NVIC) allows the bits
1539 * that define each interrupt's priority to be split between bits that
1540 * define the interrupt's pre-emption priority bits and bits that define
1541 * the interrupt's sub-priority. For simplicity all bits must be defined
1542 * to be pre-emption priority bits. The following assertion will fail if
1543 * this is not the case (if some bits represent a sub-priority).
1544 *
1545 * If the application only uses CMSIS libraries for interrupt
1546 * configuration then the correct setting can be achieved on all Cortex-M
1547 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
1548 * scheduler. Note however that some vendor specific peripheral libraries
1549 * assume a non-zero priority group setting, in which cases using a value
1550 * of zero will result in unpredicable behaviour. */
1551 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
1552 }
1553
1554 #endif /* configASSERT_DEFINED */
1555 /*-----------------------------------------------------------*/
1556
1557 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1558
vPortGrantAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1559 void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1560 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1561 {
1562 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1563 xMPU_SETTINGS * xTaskMpuSettings;
1564
1565 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1566 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1567
1568 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1569
1570 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit );
1571 }
1572
1573 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1574 /*-----------------------------------------------------------*/
1575
1576 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1577
vPortRevokeAccessToKernelObject(TaskHandle_t xInternalTaskHandle,int32_t lInternalIndexOfKernelObject)1578 void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle,
1579 int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1580 {
1581 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1582 xMPU_SETTINGS * xTaskMpuSettings;
1583
1584 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1585 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1586
1587 xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle );
1588
1589 xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit );
1590 }
1591
1592 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1593 /*-----------------------------------------------------------*/
1594
1595 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1596
1597 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
1598
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1599 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1600 {
1601 uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit;
1602 BaseType_t xAccessGranted = pdFALSE;
1603 const xMPU_SETTINGS * xTaskMpuSettings;
1604
1605 if( xSchedulerRunning == pdFALSE )
1606 {
1607 /* Grant access to all the kernel objects before the scheduler
1608 * is started. It is necessary because there is no task running
1609 * yet and therefore, we cannot use the permissions of any
1610 * task. */
1611 xAccessGranted = pdTRUE;
1612 }
1613 else
1614 {
1615 xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */
1616
1617 ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS );
1618 ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS );
1619
1620 if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG )
1621 {
1622 xAccessGranted = pdTRUE;
1623 }
1624 else
1625 {
1626 if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 )
1627 {
1628 xAccessGranted = pdTRUE;
1629 }
1630 }
1631 }
1632
1633 return xAccessGranted;
1634 }
1635
1636 #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1637
xPortIsAuthorizedToAccessKernelObject(int32_t lInternalIndexOfKernelObject)1638 BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */
1639 {
1640 ( void ) lInternalIndexOfKernelObject;
1641
1642 /* If Access Control List feature is not used, all the tasks have
1643 * access to all the kernel objects. */
1644 return pdTRUE;
1645 }
1646
1647 #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */
1648
1649 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
1650 /*-----------------------------------------------------------*/
1651
