1 /* 2 * FreeRTOS Kernel V10.6.2 3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * https://www.FreeRTOS.org 25 * https://github.com/FreeRTOS 26 * 27 */ 28 29 /* Standard includes. */ 30 #include <stdint.h> 31 32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION 33 * is defined correctly and privileged functions are placed in correct sections. */ 34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE 35 36 /* Portasm includes. */ 37 #include "portasm.h" 38 39 /* System call numbers includes. */ 40 #include "mpu_syscall_numbers.h" 41 42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the 43 * header files. */ 44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE 45 46 #if ( configENABLE_FPU == 1 ) 47 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. 48 #endif 49 50 #if ( configENABLE_MPU == 1 ) 51 vRestoreContextOfFirstTask(void)52 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 53 { 54 __asm volatile 55 ( 56 " .syntax unified \n" 57 " \n" 58 " program_mpu_first_task: \n" 59 " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 60 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ 61 " \n" 62 " dmb \n" /* Complete outstanding transfers before disabling MPU. */ 63 " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 64 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ 65 " movs r3, #1 \n" /* r3 = 1. */ 66 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ 67 " str r2, [r1] \n" /* Disable MPU. */ 68 " \n" 69 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ 70 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ 71 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ 72 " str r1, [r2] \n" /* Program MAIR0. */ 73 " \n" 74 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ 75 " ldr r1, xRNRConst2 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ 76 " \n" 77 " movs r3, #4 \n" /* r3 = 4. */ 78 " str r3, [r1] \n" /* Program RNR = 4. */ 79 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ 80 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 81 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ 82 " movs r3, #5 \n" /* r3 = 5. */ 83 " str r3, [r1] \n" /* Program RNR = 5. */ 84 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ 85 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 86 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ 87 " movs r3, #6 \n" /* r3 = 6. */ 88 " str r3, [r1] \n" /* Program RNR = 6. */ 89 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ 90 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 91 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ 92 " movs r3, #7 \n" /* r3 = 6. */ 93 " str r3, [r1] \n" /* Program RNR = 7. */ 94 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ 95 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 96 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ 97 " \n" 98 " ldr r1, xMPUCTRLConst2 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 99 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ 100 " movs r3, #1 \n" /* r3 = 1. */ 101 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ 102 " str r2, [r1] \n" /* Enable MPU. */ 103 " dsb \n" /* Force memory writes before continuing. */ 104 " \n" 105 " restore_context_first_task: \n" 106 " ldr r3, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 107 " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ 108 " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ 109 " \n" 110 " restore_special_regs_first_task: \n" 111 " subs r2, #20 \n" 112 " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ 113 " subs r2, #20 \n" 114 " msr psp, r3 \n" 115 " msr psplim, r4 \n" 116 " msr control, r5 \n" 117 " mov lr, r6 \n" 118 " ldr r4, xSecureContextConst2 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ 119 " str r0, [r4] \n" /* Restore xSecureContext. */ 120 " \n" 121 " restore_general_regs_first_task: \n" 122 " subs r2, #32 \n" 123 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ 124 " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ 125 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ 126 " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ 127 " subs r2, #48 \n" 128 " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */ 129 " mov r8, r4 \n" /* r8 = r4. */ 130 " mov r9, r5 \n" /* r9 = r5. */ 131 " mov r10, r6 \n" /* r10 = r6. */ 132 " mov r11, r7 \n" /* r11 = r7. */ 133 " subs r2, #32 \n" 134 " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */ 135 " subs r2, #16 \n" 136 " \n" 137 " restore_context_done_first_task: \n" 138 " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ 139 " bx lr \n" 140 " \n" 141 " .align 4 \n" 142 " pxCurrentTCBConst2: .word pxCurrentTCB \n" 143 " xSecureContextConst2: .word xSecureContext \n" 144 " xMPUCTRLConst2: .word 0xe000ed94 \n" 145 " xMAIR0Const2: .word 0xe000edc0 \n" 146 " xRNRConst2: .word 0xe000ed98 \n" 147 " xRBARConst2: .word 0xe000ed9c \n" 148 ); 149 } 150 151 #else /* configENABLE_MPU */ 152 vRestoreContextOfFirstTask(void)153 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 154 { 155 __asm volatile 156 ( 157 " .syntax unified \n" 158 " \n" 159 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 160 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ 161 " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ 162 " \n" 163 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ 164 " ldr r4, xSecureContextConst2 \n" 165 " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ 166 " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ 167 " movs r1, #2 \n" /* r1 = 2. */ 168 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ 169 " adds r0, #32 \n" /* Discard everything up to r0. */ 170 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ 171 " isb \n" 172 " bx r3 \n" /* Finally, branch to EXC_RETURN. */ 173 " \n" 174 " .align 4 \n" 175 "pxCurrentTCBConst2: .word pxCurrentTCB \n" 176 "xSecureContextConst2: .word xSecureContext \n" 177 ); 178 } 179 180 #endif /* configENABLE_MPU */ 181 /*-----------------------------------------------------------*/ 182 xIsPrivileged(void)183BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ 184 { 185 __asm volatile 186 ( 187 " .syntax unified \n" 188 " \n" 189 " mrs r0, control \n" /* r0 = CONTROL. */ 190 " movs r1, #1 \n" /* r1 = 1. */ 191 " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ 192 " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */ 193 " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ 194 " bx lr \n" /* Return. */ 195 " running_privileged: \n" 196 " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ 197 " bx lr \n" /* Return. */ 198 " \n" 199 " .align 4 \n" 200 ::: "r0", "r1", "memory" 201 ); 202 } 203 /*-----------------------------------------------------------*/ 204 vRaisePrivilege(void)205void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 206 { 207 __asm volatile 208 ( 209 " .syntax unified \n" 210 " \n" 211 " mrs r0, control \n" /* Read the CONTROL register. */ 212 " movs r1, #1 \n" /* r1 = 1. */ 213 " bics r0, r1 \n" /* Clear the bit 0. */ 214 " msr control, r0 \n" /* Write back the new CONTROL value. */ 215 " bx lr \n" /* Return to the caller. */ 216 ::: "r0", "r1", "memory" 217 ); 218 } 219 /*-----------------------------------------------------------*/ 220 vResetPrivilege(void)221void vResetPrivilege( void ) /* __attribute__ (( naked )) */ 222 { 223 __asm volatile 224 ( 225 " .syntax unified \n" 226 " \n" 227 " mrs r0, control \n" /* r0 = CONTROL. */ 228 " movs r1, #1 \n" /* r1 = 1. */ 229 " orrs r0, r1 \n" /* r0 = r0 | r1. */ 230 " msr control, r0 \n" /* CONTROL = r0. */ 231 " bx lr \n" /* Return to the caller. */ 232 ::: "r0", "r1", "memory" 233 ); 234 } 235 /*-----------------------------------------------------------*/ 236 vStartFirstTask(void)237void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 238 { 239 __asm volatile 240 ( 241 " .syntax unified \n" 242 " \n" 243 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */ 244 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ 245 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ 246 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ 247 " cpsie i \n" /* Globally enable interrupts. */ 248 " dsb \n" 249 " isb \n" 250 " svc %0 \n" /* System call to start the first task. */ 251 " nop \n" 252 " \n" 253 " .align 4 \n" 254 "xVTORConst: .word 0xe000ed08 \n" 255 ::"i" ( portSVC_START_SCHEDULER ) : "memory" 256 ); 257 } 258 /*-----------------------------------------------------------*/ 259 ulSetInterruptMask(void)260uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ 261 { 262 __asm volatile 263 ( 264 " .syntax unified \n" 265 " \n" 266 " mrs r0, PRIMASK \n" 267 " cpsid i \n" 268 " bx lr \n" 269 ::: "memory" 270 ); 271 } 272 /*-----------------------------------------------------------*/ 273 vClearInterruptMask(uint32_t ulMask)274void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ 275 { 276 __asm volatile 277 ( 278 " .syntax unified \n" 279 " \n" 280 " msr PRIMASK, r0 \n" 281 " bx lr \n" 282 ::: "memory" 283 ); 284 } 285 /*-----------------------------------------------------------*/ 286 287 #if ( configENABLE_MPU == 1 ) 288 PendSV_Handler(void)289 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 290 { 291 __asm volatile 292 ( 293 " .syntax unified \n" 294 " .extern SecureContext_SaveContext \n" 295 " .extern SecureContext_LoadContext \n" 296 " \n" 297 " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ 298 " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ 299 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 300 " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ 301 " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ 302 " \n" 303 " cbz r0, save_ns_context \n" /* No secure context to save. */ 304 " save_s_context: \n" 305 " push {r0-r2, lr} \n" 306 " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ 307 " pop {r0-r3} \n" /* LR is now in r3. */ 308 " mov lr, r3 \n" /* Restore LR. */ 309 " \n" 310 " save_ns_context: \n" 311 " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ 312 " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ 313 " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ 314 " \n" 315 " save_general_regs: \n" 316 " mrs r3, psp \n" 317 " stmia r2!, {r4-r7} \n" /* Store r4-r7. */ 318 " mov r4, r8 \n" /* r4 = r8. */ 319 " mov r5, r9 \n" /* r5 = r9. */ 320 " mov r6, r10 \n" /* r6 = r10. */ 321 " mov r7, r11 \n" /* r7 = r11. */ 322 " stmia r2!, {r4-r7} \n" /* Store r8-r11. */ 323 " ldmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */ 324 " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */ 325 " ldmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */ 326 " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */ 327 " \n" 328 " save_special_regs: \n" 329 " mrs r3, psp \n" /* r3 = PSP. */ 330 " mrs r4, psplim \n" /* r4 = PSPLIM. */ 331 " mrs r5, control \n" /* r5 = CONTROL. */ 332 " mov r6, lr \n" /* r6 = LR. */ 333 " stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ 334 " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ 335 " \n" 336 " select_next_task: \n" 337 " cpsid i \n" 338 " bl vTaskSwitchContext \n" 339 " cpsie i \n" 340 " \n" 341 " program_mpu: \n" 342 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 343 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ 344 " \n" 345 " dmb \n" /* Complete outstanding transfers before disabling MPU. */ 346 " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 347 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ 348 " movs r3, #1 \n" /* r3 = 1. */ 349 " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ 350 " str r2, [r1] \n" /* Disable MPU. */ 351 " \n" 352 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ 353 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ 354 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ 355 " str r1, [r2] \n" /* Program MAIR0. */ 356 " \n" 357 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ 358 " ldr r1, xRNRConst \n" /* r1 = 0xe000ed98 [Location of RNR]. */ 359 " \n" 360 " movs r3, #4 \n" /* r3 = 4. */ 361 " str r3, [r1] \n" /* Program RNR = 4. */ 362 " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ 363 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 364 " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ 365 " movs r3, #5 \n" /* r3 = 5. */ 366 " str r3, [r1] \n" /* Program RNR = 5. */ 367 " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ 368 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 369 " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ 370 " movs r3, #6 \n" /* r3 = 6. */ 371 " str r3, [r1] \n" /* Program RNR = 6. */ 372 " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ 373 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 374 " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ 375 " movs r3, #7 \n" /* r3 = 6. */ 376 " str r3, [r1] \n" /* Program RNR = 7. */ 377 " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ 378 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ 379 " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ 380 " \n" 381 " ldr r1, xMPUCTRLConst \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ 382 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ 383 " movs r3, #1 \n" /* r3 = 1. */ 384 " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ 385 " str r2, [r1] \n" /* Enable MPU. */ 386 " dsb \n" /* Force memory writes before continuing. */ 387 " \n" 388 " restore_context: \n" 389 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 390 " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ 391 " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ 392 " \n" 393 " restore_special_regs: \n" 394 " subs r2, #20 \n" 395 " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ 396 " subs r2, #20 \n" 397 " msr psp, r3 \n" 398 " msr psplim, r4 \n" 399 " msr control, r5 \n" 400 " mov lr, r6 \n" 401 " ldr r4, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ 402 " str r0, [r4] \n" /* Restore xSecureContext. */ 403 " cbz r0, restore_ns_context \n" /* No secure context to restore. */ 404 " \n" 405 " restore_s_context: \n" 406 " push {r1-r3, lr} \n" 407 " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ 408 " pop {r1-r4} \n" /* LR is now in r4. */ 409 " mov lr, r4 \n" 410 " \n" 411 " restore_ns_context: \n" 412 " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ 413 " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ 414 " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ 415 " \n" 416 " restore_general_regs: \n" 417 " subs r2, #32 \n" 418 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ 419 " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ 420 " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ 421 " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ 422 " subs r2, #48 \n" 423 " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */ 424 " mov r8, r4 \n" /* r8 = r4. */ 425 " mov r9, r5 \n" /* r9 = r5. */ 426 " mov r10, r6 \n" /* r10 = r6. */ 427 " mov r11, r7 \n" /* r11 = r7. */ 428 " subs r2, #32 \n" 429 " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */ 430 " subs r2, #16 \n" 431 " \n" 432 " restore_context_done: \n" 433 " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ 434 " bx lr \n" 435 " \n" 436 " .align 4 \n" 437 " pxCurrentTCBConst: .word pxCurrentTCB \n" 438 " xSecureContextConst: .word xSecureContext \n" 439 " xMPUCTRLConst: .word 0xe000ed94 \n" 440 " xMAIR0Const: .word 0xe000edc0 \n" 441 " xRNRConst: .word 0xe000ed98 \n" 442 " xRBARConst: .word 0xe000ed9c \n" 443 ); 444 } 445 446 #else /* configENABLE_MPU */ 447 PendSV_Handler(void)448 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 449 { 450 __asm volatile 451 ( 452 " .syntax unified \n" 453 " .extern SecureContext_SaveContext \n" 454 " .extern SecureContext_LoadContext \n" 455 " \n" 456 " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ 457 " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ 458 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 459 " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ 460 " mrs r2, psp \n" /* Read PSP in r2. */ 461 " \n" 462 " cbz r0, save_ns_context \n" /* No secure context to save. */ 463 " push {r0-r2, r14} \n" 464 " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ 465 " pop {r0-r3} \n" /* LR is now in r3. */ 466 " mov lr, r3 \n" /* LR = r3. */ 467 " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ 468 " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ 469 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 470 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ 471 " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */ 472 " str r2, [r1] \n" /* Save the new top of stack in TCB. */ 473 " mrs r1, psplim \n" /* r1 = PSPLIM. */ 474 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ 475 " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ 476 " b select_next_task \n" 477 " \n" 478 " save_ns_context: \n" 479 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 480 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ 481 " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ 482 " str r2, [r1] \n" /* Save the new top of stack in TCB. */ 483 " mrs r1, psplim \n" /* r1 = PSPLIM. */ 484 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ 485 " stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ 486 " mov r4, r8 \n" /* r4 = r8. */ 487 " mov r5, r9 \n" /* r5 = r9. */ 488 " mov r6, r10 \n" /* r6 = r10. */ 489 " mov r7, r11 \n" /* r7 = r11. */ 490 " stmia r2!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */ 491 " \n" 492 " select_next_task: \n" 493 " cpsid i \n" 494 " bl vTaskSwitchContext \n" 495 " cpsie i \n" 496 " \n" 497 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 498 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ 499 " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ 500 " \n" 501 " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ 502 " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */ 503 " mov lr, r4 \n" /* LR = r4. */ 504 " ldr r3, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ 505 " str r0, [r3] \n" /* Restore the task's xSecureContext. */ 506 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ 507 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ 508 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ 509 " push {r2, r4} \n" 510 " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ 511 " pop {r2, r4} \n" 512 " mov lr, r4 \n" /* LR = r4. */ 513 " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ 514 " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ 515 " msr psp, r2 \n" /* Remember the new top of stack for the task. */ 516 " bx lr \n" 517 " \n" 518 " restore_ns_context: \n" 519 " adds r2, r2, #16 \n" /* Move to the high registers. */ 520 " ldmia r2!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */ 521 " mov r8, r4 \n" /* r8 = r4. */ 522 " mov r9, r5 \n" /* r9 = r5. */ 523 " mov r10, r6 \n" /* r10 = r6. */ 524 " mov r11, r7 \n" /* r11 = r7. */ 525 " msr psp, r2 \n" /* Remember the new top of stack for the task. */ 526 " subs r2, r2, #32 \n" /* Go back to the low registers. */ 527 " ldmia r2!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */ 528 " bx lr \n" 529 " \n" 530 " .align 4 \n" 531 "pxCurrentTCBConst: .word pxCurrentTCB \n" 532 "xSecureContextConst: .word xSecureContext \n" 533 ); 534 } 535 536 #endif /* configENABLE_MPU */ 537 /*-----------------------------------------------------------*/ 538 539 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) 540 SVC_Handler(void)541 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 542 { 543 __asm volatile 544 ( 545 ".syntax unified \n" 546 ".extern vPortSVCHandler_C \n" 547 ".extern vSystemCallEnter \n" 548 ".extern vSystemCallExit \n" 549 " \n" 550 "movs r0, #4 \n" 551 "mov r1, lr \n" 552 "tst r0, r1 \n" 553 "beq stack_on_msp \n" 554 "stack_on_psp: \n" 555 " mrs r0, psp \n" 556 " b route_svc \n" 557 "stack_on_msp: \n" 558 " mrs r0, msp \n" 559 " b route_svc \n" 560 " \n" 561 "route_svc: \n" 562 " ldr r3, [r0, #24] \n" 563 " subs r3, #2 \n" 564 " ldrb r2, [r3, #0] \n" 565 " cmp r2, %0 \n" 566 " blt system_call_enter \n" 567 " cmp r2, %1 \n" 568 " beq system_call_exit \n" 569 " b vPortSVCHandler_C \n" 570 " \n" 571 "system_call_enter: \n" 572 " b vSystemCallEnter \n" 573 "system_call_exit: \n" 574 " b vSystemCallExit \n" 575 " \n" 576 : /* No outputs. */ 577 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) 578 : "r0", "r1", "r2", "r3", "memory" 579 ); 580 } 581 582 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ 583 SVC_Handler(void)584 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 585 { 586 __asm volatile 587 ( 588 " .syntax unified \n" 589 " \n" 590 " movs r0, #4 \n" 591 " mov r1, lr \n" 592 " tst r0, r1 \n" 593 " beq stacking_used_msp \n" 594 " mrs r0, psp \n" 595 " ldr r2, svchandler_address_const \n" 596 " bx r2 \n" 597 " stacking_used_msp: \n" 598 " mrs r0, msp \n" 599 " ldr r2, svchandler_address_const \n" 600 " bx r2 \n" 601 " \n" 602 " .align 4 \n" 603 "svchandler_address_const: .word vPortSVCHandler_C \n" 604 ); 605 } 606 607 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ 608 /*-----------------------------------------------------------*/ 609 vPortAllocateSecureContext(uint32_t ulSecureStackSize)610void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ 611 { 612 __asm volatile 613 ( 614 " .syntax unified \n" 615 " \n" 616 " svc %0 \n" /* Secure context is allocated in the supervisor call. */ 617 " bx lr \n" /* Return. */ 618 ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" 619 ); 620 } 621 /*-----------------------------------------------------------*/ 622 vPortFreeSecureContext(uint32_t * pulTCB)623void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ 624 { 625 __asm volatile 626 ( 627 " .syntax unified \n" 628 " \n" 629 " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ 630 " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ 631 " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ 632 " bne free_secure_context \n" /* Branch if r1 != 0. */ 633 " bx lr \n" /* There is no secure context (xSecureContext is NULL). */ 634 " free_secure_context: \n" 635 " svc %0 \n" /* Secure context is freed in the supervisor call. */ 636 " bx lr \n" /* Return. */ 637 ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" 638 ); 639 } 640 /*-----------------------------------------------------------*/ 641
xref:
/Kernel-v10.6.2/portable/GCC/ARM_CM23/non_secure/portasm.c
(revision ef7b253b56c9788077f5ecd6c9deb4021923d646)