1 /*
2 * FreeRTOS Kernel V10.6.2
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the ARM CM4F port.
31 *----------------------------------------------------------*/
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #ifndef __TI_VFP_SUPPORT__
38 #error This port can only be used when the project options are configured to enable hardware floating point support.
39 #endif
40
41 #if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
42 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
43 #endif
44
45 /* Constants required to manipulate the core. Registers first... */
46 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
47 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
48 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
49 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
50 /* ...then bits in the registers. */
51 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
52 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
53 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
54 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
55 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
56 #define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
57 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
58
59 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
60 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL )
61 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL )
62
63 /* Constants required to check the validity of an interrupt priority. */
64 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
65 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
66 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
67 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
68 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
69 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
70 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
71 #define portPRIGROUP_SHIFT ( 8UL )
72
73 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
74 #define portVECTACTIVE_MASK ( 0xFFUL )
75
76 /* Constants required to manipulate the VFP. */
77 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
78 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
79
80 /* Constants required to set up the initial stack. */
81 #define portINITIAL_XPSR ( 0x01000000 )
82 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
83
84 /* The systick is a 24-bit counter. */
85 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
86
87 /* A fiddle factor to estimate the number of SysTick counts that would have
88 * occurred while the SysTick counter is stopped during tickless idle
89 * calculations. */
90 #define portMISSED_COUNTS_FACTOR ( 94UL )
91
92 /* For strict compliance with the Cortex-M spec the task start address should
93 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
94 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
95
96 /* Let the user override the default SysTick clock rate. If defined by the
97 * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
98 * configuration register. */
99 #ifndef configSYSTICK_CLOCK_HZ
100 #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
101 /* Ensure the SysTick is clocked at the same frequency as the core. */
102 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
103 #else
104 /* Select the option to clock SysTick not at the same frequency as the core. */
105 #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
106 #endif
107
108 /*
109 * Setup the timer to generate the tick interrupts. The implementation in this
110 * file is weak to allow application writers to change the timer used to
111 * generate the tick interrupt.
112 */
113 void vPortSetupTimerInterrupt( void );
114
115 /*
116 * Exception handlers.
117 */
118 void xPortSysTickHandler( void );
119
120 /*
121 * Start first task is a separate function so it can be tested in isolation.
122 */
123 extern void vPortStartFirstTask( void );
124
125 /*
126 * Turn the VFP on.
127 */
128 extern void vPortEnableVFP( void );
129
130 /*
131 * Used to catch tasks that attempt to return from their implementing function.
132 */
133 static void prvTaskExitError( void );
134
135 /*-----------------------------------------------------------*/
136
137 /* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
138 * setting. */
139 const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
140
141 /* Each task maintains its own interrupt status in the critical nesting
142 * variable. */
143 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
144
145 /*
146 * The number of SysTick increments that make up one tick period.
147 */
148 #if ( configUSE_TICKLESS_IDLE == 1 )
149 static uint32_t ulTimerCountsForOneTick = 0;
150 #endif /* configUSE_TICKLESS_IDLE */
151
152 /*
153 * The maximum number of tick periods that can be suppressed is limited by the
154 * 24 bit resolution of the SysTick timer.
155 */
156 #if ( configUSE_TICKLESS_IDLE == 1 )
157 static uint32_t xMaximumPossibleSuppressedTicks = 0;
158 #endif /* configUSE_TICKLESS_IDLE */
159
160 /*
161 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
162 * power functionality only.
163 */
164 #if ( configUSE_TICKLESS_IDLE == 1 )
165 static uint32_t ulStoppedTimerCompensation = 0;
166 #endif /* configUSE_TICKLESS_IDLE */
167
168 /*
169 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
170 * FreeRTOS API functions are not called from interrupts that have been assigned
171 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
172 */
173 #if ( configASSERT_DEFINED == 1 )
174 static uint8_t ucMaxSysCallPriority = 0;
175 static uint32_t ulMaxPRIGROUPValue = 0;
176 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
177 #endif /* configASSERT_DEFINED */
178
179 /*-----------------------------------------------------------*/
180
181 /*
182 * See header file for description.
183 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)184 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
185 TaskFunction_t pxCode,
186 void * pvParameters )
187 {
188 /* Simulate the stack frame as it would be created by a context switch
189 * interrupt. */
190
191 /* Offset added to account for the way the MCU uses the stack on entry/exit
192 * of interrupts, and to ensure alignment. */
193 pxTopOfStack--;
194
195 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
196 pxTopOfStack--;
197 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
198 pxTopOfStack--;
199 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
200
201 /* Save code space by skipping register initialisation. */
202 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
203 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
204
205 /* A save method is being used that requires each task to maintain its
206 * own exec return value. */
207 pxTopOfStack--;
208 *pxTopOfStack = portINITIAL_EXC_RETURN;
209
210 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
211
212 return pxTopOfStack;
213 }
214 /*-----------------------------------------------------------*/
215
prvTaskExitError(void)216 static void prvTaskExitError( void )
217 {
218 /* A function that implements a task must not exit or attempt to return to
219 * its caller as there is nothing to return to. If a task wants to exit it
220 * should instead call vTaskDelete( NULL ).
221 *
222 * Artificially force an assert() to be triggered if configASSERT() is
223 * defined, then stop here so application writers can catch the error. */
224 configASSERT( uxCriticalNesting == ~0UL );
225 portDISABLE_INTERRUPTS();
226
227 for( ; ; )
228 {
229 }
230 }
231 /*-----------------------------------------------------------*/
232
233 /*
234 * See header file for description.
235 */
xPortStartScheduler(void)236 BaseType_t xPortStartScheduler( void )
237 {
238 #if ( configASSERT_DEFINED == 1 )
239 {
240 volatile uint8_t ucOriginalPriority;
241 volatile uint32_t ulImplementedPrioBits = 0;
242 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
243 volatile uint8_t ucMaxPriorityValue;
244
245 /* Determine the maximum priority from which ISR safe FreeRTOS API
246 * functions can be called. ISR safe functions are those that end in
247 * "FromISR". FreeRTOS maintains separate thread and ISR API functions to
248 * ensure interrupt entry is as fast and simple as possible.
249 *
250 * Save the interrupt priority value that is about to be clobbered. */
251 ucOriginalPriority = *pucFirstUserPriorityRegister;
252
253 /* Determine the number of priority bits available. First write to all
254 * possible bits. */
255 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
256
257 /* Read the value back to see how many bits stuck. */
258 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
259
260 /* Use the same mask on the maximum system call priority. */
261 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
262
263 /* Check that the maximum system call priority is nonzero after
264 * accounting for the number of priority bits supported by the
265 * hardware. A priority of 0 is invalid because setting the BASEPRI
266 * register to 0 unmasks all interrupts, and interrupts with priority 0
267 * cannot be masked using BASEPRI.
268 * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
269 configASSERT( ucMaxSysCallPriority );
270
271 /* Check that the bits not implemented in hardware are zero in
272 * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
273 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
274
275 /* Calculate the maximum acceptable priority group value for the number
276 * of bits read back. */
277
278 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
279 {
280 ulImplementedPrioBits++;
281 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
282 }
283
284 if( ulImplementedPrioBits == 8 )
285 {
286 /* When the hardware implements 8 priority bits, there is no way for
287 * the software to configure PRIGROUP to not have sub-priorities. As
288 * a result, the least significant bit is always used for sub-priority
289 * and there are 128 preemption priorities and 2 sub-priorities.
290 *
291 * This may cause some confusion in some cases - for example, if
292 * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
293 * priority interrupts will be masked in Critical Sections as those
294 * are at the same preemption priority. This may appear confusing as
295 * 4 is higher (numerically lower) priority than
296 * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
297 * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
298 * to 4, this confusion does not happen and the behaviour remains the same.
299 *
300 * The following assert ensures that the sub-priority bit in the
301 * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
302 * confusion. */
303 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
304 ulMaxPRIGROUPValue = 0;
305 }
306 else
307 {
308 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
309 }
310
311 /* Shift the priority group value back to its position within the AIRCR
312 * register. */
313 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
314 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
315
316 /* Restore the clobbered interrupt priority register to its original
317 * value. */
318 *pucFirstUserPriorityRegister = ucOriginalPriority;
319 }
320 #endif /* configASSERT_DEFINED */
321
322 /* Make PendSV and SysTick the lowest priority interrupts. */
323 portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
324 portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
325
326 /* Start the timer that generates the tick ISR. Interrupts are disabled
327 * here already. */
328 vPortSetupTimerInterrupt();
329
330 /* Initialise the critical nesting count ready for the first task. */
331 uxCriticalNesting = 0;
332
333 /* Ensure the VFP is enabled - it should be anyway. */
334 vPortEnableVFP();
335
336 /* Lazy save always. */
337 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
338
339 /* Start the first task. */
340 vPortStartFirstTask();
341
342 /* Should not get here! */
343 return 0;
344 }
345 /*-----------------------------------------------------------*/
346
vPortEndScheduler(void)347 void vPortEndScheduler( void )
348 {
349 /* Not implemented in ports where there is nothing to return to.
350 * Artificially force an assert. */
351 configASSERT( uxCriticalNesting == 1000UL );
352 }
353 /*-----------------------------------------------------------*/
354
vPortEnterCritical(void)355 void vPortEnterCritical( void )
356 {
357 portDISABLE_INTERRUPTS();
358 uxCriticalNesting++;
359
360 /* This is not the interrupt safe version of the enter critical function so
361 * assert() if it is being called from an interrupt context. Only API
362 * functions that end in "FromISR" can be used in an interrupt. Only assert if
363 * the critical nesting count is 1 to protect against recursive calls if the
364 * assert function also uses a critical section. */
365 if( uxCriticalNesting == 1 )
366 {
367 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
368 }
369 }
370 /*-----------------------------------------------------------*/
371
vPortExitCritical(void)372 void vPortExitCritical( void )
373 {
374 configASSERT( uxCriticalNesting );
375 uxCriticalNesting--;
376
377 if( uxCriticalNesting == 0 )
378 {
379 portENABLE_INTERRUPTS();
380 }
381 }
382 /*-----------------------------------------------------------*/
383
xPortSysTickHandler(void)384 void xPortSysTickHandler( void )
385 {
386 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
387 * executes all interrupts must be unmasked. There is therefore no need to
388 * save and then restore the interrupt mask value as its value is already
389 * known. */
390 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
391 {
392 /* Increment the RTOS tick. */
393 if( xTaskIncrementTick() != pdFALSE )
394 {
395 /* A context switch is required. Context switching is performed in
396 * the PendSV interrupt. Pend the PendSV interrupt. */
397 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
398 }
399 }
400 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
401 }
402 /*-----------------------------------------------------------*/
403
404 #if ( configUSE_TICKLESS_IDLE == 1 )
405
406 #pragma WEAK( vPortSuppressTicksAndSleep )
vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)407 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
408 {
409 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft;
410 TickType_t xModifiableIdleTime;
411
412 /* Make sure the SysTick reload value does not overflow the counter. */
413 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
414 {
415 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
416 }
417
418 /* Enter a critical section but don't use the taskENTER_CRITICAL()
419 * method as that will mask interrupts that should exit sleep mode. */
420 __asm( " cpsid i" );
421 __asm( " dsb" );
422 __asm( " isb" );
423
424 /* If a context switch is pending or a task is waiting for the scheduler
425 * to be unsuspended then abandon the low power entry. */
426 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
427 {
428 /* Re-enable interrupts - see comments above the cpsid instruction
429 * above. */
430 __asm( " cpsie i" );
431 }
432 else
433 {
434 /* Stop the SysTick momentarily. The time the SysTick is stopped for
435 * is accounted for as best it can be, but using the tickless mode will
436 * inevitably result in some tiny drift of the time maintained by the
437 * kernel with respect to calendar time. */
438 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
439
440 /* Use the SysTick current-value register to determine the number of
441 * SysTick decrements remaining until the next tick interrupt. If the
442 * current-value register is zero, then there are actually
443 * ulTimerCountsForOneTick decrements remaining, not zero, because the
444 * SysTick requests the interrupt when decrementing from 1 to 0. */
445 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
446
447 if( ulSysTickDecrementsLeft == 0 )
448 {
449 ulSysTickDecrementsLeft = ulTimerCountsForOneTick;
450 }
451
452 /* Calculate the reload value required to wait xExpectedIdleTime
453 * tick periods. -1 is used because this code normally executes part
454 * way through the first tick period. But if the SysTick IRQ is now
455 * pending, then clear the IRQ, suppressing the first tick, and correct
456 * the reload value to reflect that the second tick period is already
457 * underway. The expected idle time is always at least two ticks. */
458 ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
459
460 if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 )
461 {
462 portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT;
463 ulReloadValue -= ulTimerCountsForOneTick;
464 }
465
466 if( ulReloadValue > ulStoppedTimerCompensation )
467 {
468 ulReloadValue -= ulStoppedTimerCompensation;
469 }
470
471 /* Set the new reload value. */
472 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
473
474 /* Clear the SysTick count flag and set the count value back to
475 * zero. */
476 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
477
478 /* Restart SysTick. */
479 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
480
481 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
482 * set its parameter to 0 to indicate that its implementation contains
483 * its own wait for interrupt or wait for event instruction, and so wfi
484 * should not be executed again. However, the original expected idle
485 * time variable must remain unmodified, so a copy is taken. */
486 xModifiableIdleTime = xExpectedIdleTime;
487 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
488
489 if( xModifiableIdleTime > 0 )
490 {
491 __asm( " dsb" );
492 __asm( " wfi" );
493 __asm( " isb" );
494 }
495
496 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
497
498 /* Re-enable interrupts to allow the interrupt that brought the MCU
499 * out of sleep mode to execute immediately. See comments above
500 * the cpsid instruction above. */
501 __asm( " cpsie i" );
502 __asm( " dsb" );
503 __asm( " isb" );
504
505 /* Disable interrupts again because the clock is about to be stopped
506 * and interrupts that execute while the clock is stopped will increase
507 * any slippage between the time maintained by the RTOS and calendar
508 * time. */
509 __asm( " cpsid i" );
510 __asm( " dsb" );
511 __asm( " isb" );
512
513 /* Disable the SysTick clock without reading the
514 * portNVIC_SYSTICK_CTRL_REG register to ensure the
515 * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
516 * the time the SysTick is stopped for is accounted for as best it can
517 * be, but using the tickless mode will inevitably result in some tiny
518 * drift of the time maintained by the kernel with respect to calendar
519 * time*/
520 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT );
521
522 /* Determine whether the SysTick has already counted to zero. */
523 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
524 {
525 uint32_t ulCalculatedLoadValue;
526
527 /* The tick interrupt ended the sleep (or is now pending), and
528 * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG
529 * with whatever remains of the new tick period. */
530 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
531
532 /* Don't allow a tiny value, or values that have somehow
533 * underflowed because the post sleep hook did something
534 * that took too long or because the SysTick current-value register
535 * is zero. */
536 if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
537 {
538 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
539 }
540
541 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
542
543 /* As the pending tick will be processed as soon as this
544 * function exits, the tick value maintained by the tick is stepped
545 * forward by one less than the time spent waiting. */
546 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
547 }
548 else
549 {
550 /* Something other than the tick interrupt ended the sleep. */
551
552 /* Use the SysTick current-value register to determine the
553 * number of SysTick decrements remaining until the expected idle
554 * time would have ended. */
555 ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG;
556 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT )
557 {
558 /* If the SysTick is not using the core clock, the current-
559 * value register might still be zero here. In that case, the
560 * SysTick didn't load from the reload register, and there are
561 * ulReloadValue decrements remaining in the expected idle
562 * time, not zero. */
563 if( ulSysTickDecrementsLeft == 0 )
564 {
565 ulSysTickDecrementsLeft = ulReloadValue;
566 }
567 }
568 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
569
570 /* Work out how long the sleep lasted rounded to complete tick
571 * periods (not the ulReload value which accounted for part
572 * ticks). */
573 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft;
574
575 /* How many complete tick periods passed while the processor
576 * was waiting? */
577 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
578
579 /* The reload value is set to whatever fraction of a single tick
580 * period remains. */
581 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
582 }
583
584 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again,
585 * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If
586 * the SysTick is not using the core clock, temporarily configure it to
587 * use the core clock. This configuration forces the SysTick to load
588 * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next
589 * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready
590 * to receive the standard value immediately. */
591 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
592 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
593 #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT )
594 {
595 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
596 }
597 #else
598 {
599 /* The temporary usage of the core clock has served its purpose,
600 * as described above. Resume usage of the other clock. */
601 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
602
603 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
604 {
605 /* The partial tick period already ended. Be sure the SysTick
606 * counts it only once. */
607 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0;
608 }
609
610 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
611 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
612 }
613 #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */
614
615 /* Step the tick to account for any tick periods that elapsed. */
616 vTaskStepTick( ulCompleteTickPeriods );
617
618 /* Exit with interrupts enabled. */
619 __asm( " cpsie i" );
620 }
621 }
622
623 #endif /* configUSE_TICKLESS_IDLE */
624 /*-----------------------------------------------------------*/
625
626 /*
627 * Setup the systick timer to generate the tick interrupts at the required
628 * frequency.
629 */
630 #pragma WEAK( vPortSetupTimerInterrupt )
vPortSetupTimerInterrupt(void)631 void vPortSetupTimerInterrupt( void )
632 {
633 /* Calculate the constants required to configure the tick interrupt. */
634 #if ( configUSE_TICKLESS_IDLE == 1 )
635 {
636 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
637 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
638 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
639 }
640 #endif /* configUSE_TICKLESS_IDLE */
641
642 /* Stop and clear the SysTick. */
643 portNVIC_SYSTICK_CTRL_REG = 0UL;
644 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
645
646 /* Configure SysTick to interrupt at the requested rate. */
647 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
648 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
649 }
650 /*-----------------------------------------------------------*/
651
652 #if ( configASSERT_DEFINED == 1 )
653
vPortValidateInterruptPriority(void)654 void vPortValidateInterruptPriority( void )
655 {
656 extern uint32_t ulPortGetIPSR( void );
657 uint32_t ulCurrentInterrupt;
658 uint8_t ucCurrentPriority;
659
660 ulCurrentInterrupt = ulPortGetIPSR();
661
662 /* Is the interrupt number a user defined interrupt? */
663 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
664 {
665 /* Look up the interrupt's priority. */
666 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
667
668 /* The following assertion will fail if a service routine (ISR) for
669 * an interrupt that has been assigned a priority above
670 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
671 * function. ISR safe FreeRTOS API functions must *only* be called
672 * from interrupts that have been assigned a priority at or below
673 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
674 *
675 * Numerically low interrupt priority numbers represent logically high
676 * interrupt priorities, therefore the priority of the interrupt must
677 * be set to a value equal to or numerically *higher* than
678 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
679 *
680 * Interrupts that use the FreeRTOS API must not be left at their
681 * default priority of zero as that is the highest possible priority,
682 * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
683 * and therefore also guaranteed to be invalid.
684 *
685 * FreeRTOS maintains separate thread and ISR API functions to ensure
686 * interrupt entry is as fast and simple as possible.
687 *
688 * The following links provide detailed information:
689 * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
690 * https://www.FreeRTOS.org/FAQHelp.html */
691 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
692 }
693
694 /* Priority grouping: The interrupt controller (NVIC) allows the bits
695 * that define each interrupt's priority to be split between bits that
696 * define the interrupt's pre-emption priority bits and bits that define
697 * the interrupt's sub-priority. For simplicity all bits must be defined
698 * to be pre-emption priority bits. The following assertion will fail if
699 * this is not the case (if some bits represent a sub-priority).
700 *
701 * If the application only uses CMSIS libraries for interrupt
702 * configuration then the correct setting can be achieved on all Cortex-M
703 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
704 * scheduler. Note however that some vendor specific peripheral libraries
705 * assume a non-zero priority group setting, in which cases using a value
706 * of zero will result in unpredictable behaviour. */
707 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
708 }
709
710 #endif /* configASSERT_DEFINED */
711
