1 /* 2 * FreeRTOS+TCP <DEVELOPMENT BRANCH> 3 * Copyright (C) 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * http://aws.amazon.com/freertos 25 * http://www.FreeRTOS.org 26 */ 27 28 /** 29 * @brief 30 * Handling of Ethernet PHY's 31 * PHY's communicate with an EMAC either through 32 * a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII). 33 * The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports 34 * shall be treated independently. 35 * 36 */ 37 38 #ifndef PHYHANDLING_H 39 40 #define PHYHANDLING_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 47 #ifndef ipconfigPHY_MAX_PORTS 48 /* There can be at most 32 PHY ports, but in most cases there are 4 or less. */ 49 #define ipconfigPHY_MAX_PORTS 4 50 #endif 51 52 /* A generic user-provided function that reads from the PHY-port at 'xAddress'( 0-based ). A 16-bit value shall be stored in 53 * '*pulValue'. xRegister is the register number ( 0 .. 31 ). In fact all PHY registers are 16-bit. 54 * Return non-zero in case the action failed. */ 55 typedef BaseType_t ( * xApplicationPhyReadHook_t )( BaseType_t xAddress, 56 BaseType_t xRegister, 57 uint32_t * pulValue ); 58 59 /* A generic user-provided function that writes 'ulValue' to the 60 * PHY-port at 'xAddress' ( 0-based ). xRegister is the register number ( 0 .. 31 ). 61 * Return non-zero in case the action failed. */ 62 typedef BaseType_t ( * xApplicationPhyWriteHook_t )( BaseType_t xAddress, 63 BaseType_t xRegister, 64 uint32_t ulValue ); 65 66 typedef struct xPhyProperties 67 { 68 uint8_t ucSpeed; 69 uint8_t ucMDI_X; /* MDI-X : Medium Dependent Interface - Crossover */ 70 uint8_t ucDuplex; 71 uint8_t ucSpare; 72 } PhyProperties_t; 73 74 typedef struct xEthernetPhy 75 { 76 xApplicationPhyReadHook_t fnPhyRead; 77 xApplicationPhyWriteHook_t fnPhyWrite; 78 uint32_t ulPhyIDs[ ipconfigPHY_MAX_PORTS ]; 79 uint8_t ucPhyIndexes[ ipconfigPHY_MAX_PORTS ]; 80 TimeOut_t xLinkStatusTimer; 81 TickType_t xLinkStatusRemaining; 82 BaseType_t xPortCount; 83 uint32_t ulBCRValue; 84 uint32_t ulACRValue; 85 uint32_t ulLinkStatusMask; 86 PhyProperties_t xPhyPreferences; 87 PhyProperties_t xPhyProperties; 88 } EthernetPhy_t; 89 90 /* Some defines used internally here to indicate preferences about speed, MDIX 91 * (wired direct or crossed), and duplex (half or full). */ 92 93 /* Values for PhyProperties_t::ucSpeed : */ 94 #define PHY_SPEED_10 1 95 #define PHY_SPEED_100 2 96 #define PHY_SPEED_AUTO 3 97 98 /* Values for PhyProperties_t::ucMDI_X : */ 99 #define PHY_MDIX_DIRECT 1 100 #define PHY_MDIX_CROSSED 2 101 #define PHY_MDIX_AUTO 3 102 103 /* Values for PhyProperties_t::ucDuplex : */ 104 #define PHY_DUPLEX_HALF 1 105 #define PHY_DUPLEX_FULL 2 106 #define PHY_DUPLEX_AUTO 3 107 108 /* ID's of supported PHY's : */ 109 #define PHY_ID_LAN8742A 0x0007c130 110 #define PHY_ID_LAN8720 0x0007c0f0 111 112 #define PHY_ID_KSZ8041 0x000010A1 113 #define PHY_ID_KSZ8051 0x000010A1 114 #define PHY_ID_KSZ8081 0x000010A1 115 116 #define PHY_ID_KSZ8863 0x00221430 117 #define PHY_ID_KSZ8795 0x00221550 118 #define PHY_ID_KSZ8081MNXIA 0x00221560 119 120 #define PHY_ID_DP83848I 0x20005C90 121 #define PHY_ID_DP83TC811S 0x2000A250 122 123 #define PHY_ID_TM4C129X 0x2000A221 124 125 #define PHY_ID_MV88E6071 0xFF000710 126 127 /* Initialise the struct and assign a PHY-read and -write function. */ 128 void vPhyInitialise( EthernetPhy_t * pxPhyObject, 129 xApplicationPhyReadHook_t fnPhyRead, 130 xApplicationPhyWriteHook_t fnPhyWrite ); 131 132 /* Discover all PHY's connected by polling 32 indexes ( zero-based ) */ 133 BaseType_t xPhyDiscover( EthernetPhy_t * pxPhyObject ); 134 135 /* Send a reset command to the connected PHY ports and send configuration. */ 136 BaseType_t xPhyConfigure( EthernetPhy_t * pxPhyObject, 137 const PhyProperties_t * pxPhyProperties ); 138 139 /* Give a command to start auto negotiation on a set of PHY port's. */ 140 BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t * pxPhyObject, 141 uint32_t ulPhyMask ); 142 143 /* Do not use auto negotiation but use predefined values from 'pxPhyObject->xPhyPreferences'. */ 144 BaseType_t xPhyFixedValue( EthernetPhy_t * pxPhyObject, 145 uint32_t ulPhyMask ); 146 147 /* Check the current Link Status. 148 * 'xHadReception' : make this true if a packet has been received since the 149 * last call to this function. */ 150 BaseType_t xPhyCheckLinkStatus( EthernetPhy_t * pxPhyObject, 151 BaseType_t xHadReception ); 152 153 /* Get the bitmask of a given 'EthernetPhy_t'. */ 154 #define xPhyGetMask( pxPhyObject ) \ 155 ( ( ( ( uint32_t ) 1u ) << ( pxPhyObject )->xPortCount ) - 1u ) 156 157 #ifdef __cplusplus 158 } /* extern "C" */ 159 #endif 160 161 #endif /* ifndef PHYHANDLING_H */ 162