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Searched refs:portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE (Results 1 – 25 of 42) sorted by relevance

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/Kernel-v11.1.0/portable/IAR/ARM_CM55/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM85/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM23/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
Dport.c891 …portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & … in prvSetupMPU()
1805 …xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS )… in vPortStoreTaskMPUSettings()
/Kernel-v11.1.0/portable/IAR/ARM_CM55_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM55/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/ARMv8M/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM85_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM35P/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM35P_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM33/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM35P_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
Dport.c891 …portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & … in prvSetupMPU()
1805 …xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS )… in vPortStoreTaskMPUSettings()
/Kernel-v11.1.0/portable/IAR/ARM_CM33_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
Dport.c891 …portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & … in prvSetupMPU()
1805 …xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS )… in vPortStoreTaskMPUSettings()
/Kernel-v11.1.0/portable/GCC/ARM_CM23/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM23_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM23_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM55_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM85_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM85/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/GCC/ARM_CM33/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
/Kernel-v11.1.0/portable/IAR/ARM_CM35P/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro
Dport.c891 …portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & … in prvSetupMPU()
1805 …xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS )… in vPortStoreTaskMPUSettings()
/Kernel-v11.1.0/portable/GCC/ARM_CM33_NTZ/non_secure/
Dportmacrocommon.h174 #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, … macro

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