| /Kernel-v10.6.2/portable/GCC/MicroBlaze/ |
| D | portasm.s | 41 addik r1, r1, -132
43 swi r31, r1, 4
47 swi r30, r1, 12
48 swi r29, r1, 16
49 swi r28, r1, 20
50 swi r27, r1, 24
51 swi r26, r1, 28
52 swi r25, r1, 32
53 swi r24, r1, 36
54 swi r23, r1, 40
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM23/non_secure/ |
| D | mpu_wrappers_v2_asm.S | 47 push {r0, r1}
49 movs r1, #1
50 tst r0, r1
53 pop {r0, r1}
56 pop {r0, r1}
62 push {r0, r1}
64 movs r1, #1
65 tst r0, r1
68 pop {r0, r1}
71 pop {r0, r1}
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM23_NTZ/non_secure/ |
| D | mpu_wrappers_v2_asm.S | 47 push {r0, r1}
49 movs r1, #1
50 tst r0, r1
53 pop {r0, r1}
56 pop {r0, r1}
62 push {r0, r1}
64 movs r1, #1
65 tst r0, r1
68 pop {r0, r1}
71 pop {r0, r1}
[all …]
|
| D | portasm.s | 75 movs r1, #1 /* r1 = 1. */
76 …tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions…
88 movs r1, #1 /* r1 = 1. */
89 orrs r0, r1 /* r0 = r0 | r1. */
110 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
111 ldr r2, [r1] /* Read the value of MPU_CTRL. */
114 str r2, [r1] /* Disable MPU. */
117 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
119 str r1, [r2] /* Program MAIR0. */
122 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
[all …]
|
| /Kernel-v10.6.2/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/ |
| D | mpu_wrappers_v2_asm.S | 47 push {r0, r1}
49 movs r1, #1
50 tst r0, r1
53 pop {r0, r1}
56 pop {r0, r1}
62 push {r0, r1}
64 movs r1, #1
65 tst r0, r1
68 pop {r0, r1}
71 pop {r0, r1}
[all …]
|
| /Kernel-v10.6.2/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/ |
| D | mpu_wrappers_v2_asm.S | 47 push {r0, r1}
49 movs r1, #1
50 tst r0, r1
53 pop {r0, r1}
56 pop {r0, r1}
62 push {r0, r1}
64 movs r1, #1
65 tst r0, r1
68 pop {r0, r1}
71 pop {r0, r1}
[all …]
|
| D | portasm.s | 75 movs r1, #1 /* r1 = 1. */
76 …tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions…
88 movs r1, #1 /* r1 = 1. */
89 orrs r0, r1 /* r0 = r0 | r1. */
110 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
111 ldr r2, [r1] /* Read the value of MPU_CTRL. */
114 str r2, [r1] /* Disable MPU. */
117 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
119 str r1, [r2] /* Program MAIR0. */
122 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
[all …]
|
| /Kernel-v10.6.2/portable/GCC/MicroBlazeV8/ |
| D | portasm.S | 99 addik r1, r1, portMINUS_CONTEXT_SIZE
102 swi r31, r1, portR31_OFFSET
103 swi r30, r1, portR30_OFFSET
104 swi r29, r1, portR29_OFFSET
105 swi r28, r1, portR28_OFFSET
106 swi r27, r1, portR27_OFFSET
107 swi r26, r1, portR26_OFFSET
108 swi r25, r1, portR25_OFFSET
109 swi r24, r1, portR24_OFFSET
110 swi r23, r1, portR23_OFFSET
[all …]
|
| /Kernel-v10.6.2/portable/GCC/MicroBlazeV9/ |
| D | portasm.S | 113 addik r1, r1, portMINUS_CONTEXT_SIZE
116 swi r31, r1, portR31_OFFSET
117 swi r30, r1, portR30_OFFSET
118 swi r29, r1, portR29_OFFSET
119 swi r28, r1, portR28_OFFSET
120 swi r27, r1, portR27_OFFSET
121 swi r26, r1, portR26_OFFSET
122 swi r25, r1, portR25_OFFSET
123 swi r24, r1, portR24_OFFSET
124 swi r23, r1, portR23_OFFSET
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM85_NTZ/non_secure/ |
| D | portasm.s | 101 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
102 ldr r2, [r1] /* Read the value of MPU_CTRL. */
104 str r2, [r1] /* Disable MPU. */
107 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
109 str r1, [r2] /* Program MAIR0. */
112 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
116 str r3, [r1] /* Program RNR = 4. */
122 str r3, [r1] /* Program RNR = 8. */
126 str r3, [r1] /* Program RNR = 12. */
131 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM35P_NTZ/non_secure/ |
| D | portasm.s | 101 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
102 ldr r2, [r1] /* Read the value of MPU_CTRL. */
104 str r2, [r1] /* Disable MPU. */
107 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
109 str r1, [r2] /* Program MAIR0. */
112 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
116 str r3, [r1] /* Program RNR = 4. */
122 str r3, [r1] /* Program RNR = 8. */
126 str r3, [r1] /* Program RNR = 12. */
131 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM33_NTZ/non_secure/ |
| D | portasm.s | 101 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
102 ldr r2, [r1] /* Read the value of MPU_CTRL. */
104 str r2, [r1] /* Disable MPU. */
107 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
109 str r1, [r2] /* Program MAIR0. */
112 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
116 str r3, [r1] /* Program RNR = 4. */
122 str r3, [r1] /* Program RNR = 8. */
126 str r3, [r1] /* Program RNR = 12. */
131 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/ |
| D | portasm.s | 101 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
102 ldr r2, [r1] /* Read the value of MPU_CTRL. */
104 str r2, [r1] /* Disable MPU. */
107 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
109 str r1, [r2] /* Program MAIR0. */
112 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
116 str r3, [r1] /* Program RNR = 4. */
122 str r3, [r1] /* Program RNR = 8. */
126 str r3, [r1] /* Program RNR = 12. */
131 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM55_NTZ/non_secure/ |
| D | portasm.s | 101 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
102 ldr r2, [r1] /* Read the value of MPU_CTRL. */
104 str r2, [r1] /* Disable MPU. */
107 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
109 str r1, [r2] /* Program MAIR0. */
112 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
116 str r3, [r1] /* Program RNR = 4. */
122 str r3, [r1] /* Program RNR = 8. */
126 str r3, [r1] /* Program RNR = 12. */
131 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM23/secure/ |
| D | secure_context_port_asm.s | 49 mrs r1, ipsr /* r1 = IPSR. */
50 cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
51 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureCont…
54 … ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
59 msr psp, r1 /* PSP = r1. */
67 mrs r1, ipsr /* r1 = IPSR. */
68 cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
69 mrs r1, psp /* r1 = PSP. */
73 subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
74 …str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentSt…
[all …]
|
| /Kernel-v10.6.2/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/ |
| D | secure_context_port_asm.s | 49 mrs r1, ipsr /* r1 = IPSR. */
50 cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
51 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureCont…
54 … ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
59 msr psp, r1 /* PSP = r1. */
67 mrs r1, ipsr /* r1 = IPSR. */
68 cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
69 mrs r1, psp /* r1 = PSP. */
73 subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
74 …str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentSt…
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM55/secure/ |
| D | secure_context_port_asm.s | 45 mrs r1, ipsr /* r1 = IPSR. */
46 …cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
47 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecure…
50 …ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL…
55 msr psp, r1 /* PSP = r1. */
63 mrs r1, ipsr /* r1 = IPSR. */
64 …cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
65 mrs r1, psp /* r1 = PSP. */
68 vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
69 vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM85/secure/ |
| D | secure_context_port_asm.s | 45 mrs r1, ipsr /* r1 = IPSR. */
46 …cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
47 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecure…
50 …ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL…
55 msr psp, r1 /* PSP = r1. */
63 mrs r1, ipsr /* r1 = IPSR. */
64 …cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
65 mrs r1, psp /* r1 = PSP. */
68 vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
69 vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM35P/secure/ |
| D | secure_context_port_asm.s | 45 mrs r1, ipsr /* r1 = IPSR. */
46 …cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
47 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecure…
50 …ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL…
55 msr psp, r1 /* PSP = r1. */
63 mrs r1, ipsr /* r1 = IPSR. */
64 …cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
65 mrs r1, psp /* r1 = PSP. */
68 vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
69 vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM33/secure/ |
| D | secure_context_port_asm.s | 45 mrs r1, ipsr /* r1 = IPSR. */
46 …cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
47 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecure…
50 …ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL…
55 msr psp, r1 /* PSP = r1. */
63 mrs r1, ipsr /* r1 = IPSR. */
64 …cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
65 mrs r1, psp /* r1 = PSP. */
68 vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
69 vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
[all …]
|
| /Kernel-v10.6.2/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/ |
| D | secure_context_port_asm.s | 45 mrs r1, ipsr /* r1 = IPSR. */
46 …cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
47 …ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecure…
50 …ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL…
55 msr psp, r1 /* PSP = r1. */
63 mrs r1, ipsr /* r1 = IPSR. */
64 …cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. …
65 mrs r1, psp /* r1 = PSP. */
68 vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
69 vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM55/non_secure/ |
| D | portasm.s | 111 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
112 ldr r2, [r1] /* Read the value of MPU_CTRL. */
114 str r2, [r1] /* Disable MPU. */
117 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
119 str r1, [r2] /* Program MAIR0. */
122 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
126 str r3, [r1] /* Program RNR = 4. */
132 str r3, [r1] /* Program RNR = 8. */
136 str r3, [r1] /* Program RNR = 12. */
141 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM85/non_secure/ |
| D | portasm.s | 111 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
112 ldr r2, [r1] /* Read the value of MPU_CTRL. */
114 str r2, [r1] /* Disable MPU. */
117 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
119 str r1, [r2] /* Program MAIR0. */
122 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
126 str r3, [r1] /* Program RNR = 4. */
132 str r3, [r1] /* Program RNR = 8. */
136 str r3, [r1] /* Program RNR = 12. */
141 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM35P/non_secure/ |
| D | portasm.s | 111 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
112 ldr r2, [r1] /* Read the value of MPU_CTRL. */
114 str r2, [r1] /* Disable MPU. */
117 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
119 str r1, [r2] /* Program MAIR0. */
122 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
126 str r3, [r1] /* Program RNR = 4. */
132 str r3, [r1] /* Program RNR = 8. */
136 str r3, [r1] /* Program RNR = 12. */
141 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
| /Kernel-v10.6.2/portable/IAR/ARM_CM33/non_secure/ |
| D | portasm.s | 111 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
112 ldr r2, [r1] /* Read the value of MPU_CTRL. */
114 str r2, [r1] /* Disable MPU. */
117 ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
119 str r1, [r2] /* Program MAIR0. */
122 ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
126 str r3, [r1] /* Program RNR = 4. */
132 str r3, [r1] /* Program RNR = 8. */
136 str r3, [r1] /* Program RNR = 12. */
141 ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
[all …]
|
