1 /*
2 * FreeRTOS Kernel V11.1.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31 #include <string.h>
32
33 /* Scheduler includes. */
34 #include "FreeRTOS.h"
35 #include "task.h"
36
37 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
38 #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
39 #endif
40
41 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
42 #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
43 #endif
44
45 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
46 #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
47 #endif
48
49 #ifndef configSETUP_TICK_INTERRUPT
50 #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
51 #endif /* configSETUP_TICK_INTERRUPT */
52
53 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
54 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
55 #endif
56
57 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
58 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
59 #endif
60
61 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
62 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
63 #endif
64
65 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
66 /* Check the configuration. */
67 #if ( configMAX_PRIORITIES > 32 )
68 #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
69 #endif
70 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
71
72 /* In case security extensions are implemented. */
73 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
74 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
75 #endif
76
77 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
78 * portmacro.h. */
79 #ifndef configCLEAR_TICK_INTERRUPT
80 #define configCLEAR_TICK_INTERRUPT()
81 #endif
82
83 /* A critical section is exited when the critical section nesting count reaches
84 * this value. */
85 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
86
87 /* In all GICs 255 can be written to the priority mask register to unmask all
88 * (but the lowest) interrupt priority. */
89 #define portUNMASK_VALUE ( 0xFFUL )
90
91 /* Tasks are not created with a floating point context, but can be given a
92 * floating point context after they have been created. A variable is stored as
93 * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
94 * does not have an FPU context, or any other value if the task does have an FPU
95 * context. */
96 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
97
98 /* Constants required to setup the initial task context. */
99 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
100 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
101 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
102 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
103
104 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
105 * point is zero. */
106 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
107
108 /* Masks all bits in the APSR other than the mode bits. */
109 #define portAPSR_MODE_BITS_MASK ( 0x1F )
110
111 /* The value of the mode bits in the APSR when the CPU is executing in user
112 * mode. */
113 #define portAPSR_USER_MODE ( 0x10 )
114
115 /* The critical section macros only mask interrupts up to an application
116 * determined priority level. Sometimes it is necessary to turn interrupt off in
117 * the CPU itself before modifying certain hardware registers. */
118 #define portCPU_IRQ_DISABLE() \
119 __asm volatile ( "CPSID i" ::: "memory" ); \
120 __asm volatile ( "DSB" ); \
121 __asm volatile ( "ISB" );
122
123 #define portCPU_IRQ_ENABLE() \
124 __asm volatile ( "CPSIE i" ::: "memory" ); \
125 __asm volatile ( "DSB" ); \
126 __asm volatile ( "ISB" );
127
128
129 /* Macro to unmask all interrupt priorities. */
130 #define portCLEAR_INTERRUPT_MASK() \
131 { \
132 portCPU_IRQ_DISABLE(); \
133 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
134 __asm volatile ( "DSB \n" \
135 "ISB \n" ); \
136 portCPU_IRQ_ENABLE(); \
137 }
138
139 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
140 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
141 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
142
143 /* Let the user override the pre-loading of the initial LR with the address of
144 * prvTaskExitError() in case it messes up unwinding of the stack in the
145 * debugger. */
146 #ifdef configTASK_RETURN_ADDRESS
147 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
148 #else
149 #define portTASK_RETURN_ADDRESS prvTaskExitError
150 #endif
151
152 /* The space on the stack required to hold the FPU registers. This is 32 64-bit
153 * registers, plus a 32-bit status register. */
154 #define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 )
155
156 /*-----------------------------------------------------------*/
157
158 /*
159 * Starts the first task executing. This function is necessarily written in
160 * assembly code so is implemented in portASM.s.
161 */
162 extern void vPortRestoreTaskContext( void );
163
164 /*
165 * Used to catch tasks that attempt to return from their implementing function.
166 */
167 static void prvTaskExitError( void );
168
169 /*
170 * If the application provides an implementation of vApplicationIRQHandler(),
171 * then it will get called directly without saving the FPU registers on
172 * interrupt entry, and this weak implementation of
173 * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
174 * it should never actually get called so its implementation contains a
175 * call to configASSERT() that will always fail.
176 *
177 * If the application provides its own implementation of
178 * vApplicationFPUSafeIRQHandler() then the implementation of
179 * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
180 * before calling it.
181 *
182 * Therefore, if the application writer wants FPU registers to be saved on
183 * interrupt entry their IRQ handler must be called
184 * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
185 * FPU registers to be saved on interrupt entry their IRQ handler must be
186 * called vApplicationIRQHandler().
187 */
188 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) );
189
190 /*-----------------------------------------------------------*/
191
192 /* A variable is used to keep track of the critical section nesting. This
193 * variable has to be stored as part of the task context and must be initialised to
194 * a non zero value to ensure interrupts don't inadvertently become unmasked before
195 * the scheduler starts. As it is stored as part of the task context it will
196 * automatically be set to 0 when the first task is started. */
197 volatile uint32_t ulCriticalNesting = 9999UL;
198
199 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
200 * a floating point context must be saved and restored for the task. */
201 volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
202
203 /* Set to 1 to pend a context switch from an ISR. */
204 volatile uint32_t ulPortYieldRequired = pdFALSE;
205
206 /* Counts the interrupt nesting depth. A context switch is only performed if
207 * if the nesting depth is 0. */
208 volatile uint32_t ulPortInterruptNesting = 0UL;
209
210 /* Used in the asm file. */
211 __attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
212 __attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
213 __attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
214 __attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
215
216 /*-----------------------------------------------------------*/
217
218 /*
219 * See header file for description.
220 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)221 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
222 TaskFunction_t pxCode,
223 void * pvParameters )
224 {
225 /* Setup the initial stack of the task. The stack is set exactly as
226 * expected by the portRESTORE_CONTEXT() macro.
227 *
228 * The fist real value on the stack is the status register, which is set for
229 * system mode, with interrupts enabled. A few NULLs are added first to ensure
230 * GDB does not try decoding a non-existent return address. */
231 *pxTopOfStack = ( StackType_t ) NULL;
232 pxTopOfStack--;
233 *pxTopOfStack = ( StackType_t ) NULL;
234 pxTopOfStack--;
235 *pxTopOfStack = ( StackType_t ) NULL;
236 pxTopOfStack--;
237 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
238
239 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
240 {
241 /* The task will start in THUMB mode. */
242 *pxTopOfStack |= portTHUMB_MODE_BIT;
243 }
244
245 pxTopOfStack--;
246
247 /* Next the return address, which in this case is the start of the task. */
248 *pxTopOfStack = ( StackType_t ) pxCode;
249 pxTopOfStack--;
250
251 /* Next all the registers other than the stack pointer. */
252 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
253 pxTopOfStack--;
254 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
255 pxTopOfStack--;
256 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
257 pxTopOfStack--;
258 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
259 pxTopOfStack--;
260 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
261 pxTopOfStack--;
262 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
263 pxTopOfStack--;
264 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
265 pxTopOfStack--;
266 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
267 pxTopOfStack--;
268 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
269 pxTopOfStack--;
270 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
271 pxTopOfStack--;
272 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
273 pxTopOfStack--;
274 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
275 pxTopOfStack--;
276 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
277 pxTopOfStack--;
278 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
279 pxTopOfStack--;
280
281 /* The task will start with a critical nesting count of 0 as interrupts are
282 * enabled. */
283 *pxTopOfStack = portNO_CRITICAL_NESTING;
284
285 #if ( configUSE_TASK_FPU_SUPPORT == 1 )
286 {
287 /* The task will start without a floating point context. A task that
288 * uses the floating point hardware must call vPortTaskUsesFPU() before
289 * executing any floating point instructions. */
290 pxTopOfStack--;
291 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
292 }
293 #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
294 {
295 /* The task will start with a floating point context. Leave enough
296 * space for the registers - and ensure they are initialised to 0. */
297 pxTopOfStack -= portFPU_REGISTER_WORDS;
298 memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
299
300 pxTopOfStack--;
301 *pxTopOfStack = pdTRUE;
302 ulPortTaskHasFPUContext = pdTRUE;
303 }
304 #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
305 {
306 #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
307 }
308 #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
309
310 return pxTopOfStack;
311 }
312 /*-----------------------------------------------------------*/
313
prvTaskExitError(void)314 static void prvTaskExitError( void )
315 {
316 /* A function that implements a task must not exit or attempt to return to
317 * its caller as there is nothing to return to. If a task wants to exit it
318 * should instead call vTaskDelete( NULL ).
319 *
320 * Artificially force an assert() to be triggered if configASSERT() is
321 * defined, then stop here so application writers can catch the error. */
322 configASSERT( ulPortInterruptNesting == ~0UL );
323 portDISABLE_INTERRUPTS();
324
325 for( ; ; )
326 {
327 }
328 }
329 /*-----------------------------------------------------------*/
330
xPortStartScheduler(void)331 BaseType_t xPortStartScheduler( void )
332 {
333 uint32_t ulAPSR;
334
335 #if ( configASSERT_DEFINED == 1 )
336 {
337 volatile uint8_t ucOriginalPriority;
338 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
339 volatile uint8_t ucMaxPriorityValue;
340
341 /* Determine how many priority bits are implemented in the GIC.
342 *
343 * Save the interrupt priority value that is about to be clobbered. */
344 ucOriginalPriority = *pucFirstUserPriorityRegister;
345
346 /* Determine the number of priority bits available. First write to
347 * all possible bits. */
348 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
349
350 /* Read the value back to see how many bits stuck. */
351 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
352
353 /* Shift to the least significant bits. */
354 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
355 {
356 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
357 }
358
359 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
360 * value. */
361 configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
362
363 /* Restore the clobbered interrupt priority register to its original
364 * value. */
365 *pucFirstUserPriorityRegister = ucOriginalPriority;
366 }
367 #endif /* configASSERT_DEFINED */
368
369
370 /* Only continue if the CPU is not in User mode. The CPU must be in a
371 * Privileged mode for the scheduler to start. */
372 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
373 ulAPSR &= portAPSR_MODE_BITS_MASK;
374 configASSERT( ulAPSR != portAPSR_USER_MODE );
375
376 if( ulAPSR != portAPSR_USER_MODE )
377 {
378 /* Only continue if the binary point value is set to its lowest possible
379 * setting. See the comments in vPortValidateInterruptPriority() below for
380 * more information. */
381 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
382
383 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
384 {
385 /* Interrupts are turned off in the CPU itself to ensure tick does
386 * not execute while the scheduler is being started. Interrupts are
387 * automatically turned back on in the CPU when the first task starts
388 * executing. */
389 portCPU_IRQ_DISABLE();
390
391 /* Start the timer that generates the tick ISR. */
392 configSETUP_TICK_INTERRUPT();
393
394 /* Start the first task executing. */
395 vPortRestoreTaskContext();
396 }
397 }
398
399 /* Will only get here if vTaskStartScheduler() was called with the CPU in
400 * a non-privileged mode or the binary point register was not set to its lowest
401 * possible value. prvTaskExitError() is referenced to prevent a compiler
402 * warning about it being defined but not referenced in the case that the user
403 * defines their own exit address. */
404 ( void ) prvTaskExitError;
405 return 0;
406 }
407 /*-----------------------------------------------------------*/
408
vPortEndScheduler(void)409 void vPortEndScheduler( void )
410 {
411 /* Not implemented in ports where there is nothing to return to.
412 * Artificially force an assert. */
413 configASSERT( ulCriticalNesting == 1000UL );
414 }
415 /*-----------------------------------------------------------*/
416
vPortEnterCritical(void)417 void vPortEnterCritical( void )
418 {
419 /* Mask interrupts up to the max syscall interrupt priority. */
420 ulPortSetInterruptMask();
421
422 /* Now that interrupts are disabled, ulCriticalNesting can be accessed
423 * directly. Increment ulCriticalNesting to keep a count of how many times
424 * portENTER_CRITICAL() has been called. */
425 ulCriticalNesting++;
426
427 /* This is not the interrupt safe version of the enter critical function so
428 * assert() if it is being called from an interrupt context. Only API
429 * functions that end in "FromISR" can be used in an interrupt. Only assert if
430 * the critical nesting count is 1 to protect against recursive calls if the
431 * assert function also uses a critical section. */
432 if( ulCriticalNesting == 1 )
433 {
434 configASSERT( ulPortInterruptNesting == 0 );
435 }
436 }
437 /*-----------------------------------------------------------*/
438
vPortExitCritical(void)439 void vPortExitCritical( void )
440 {
441 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
442 {
443 /* Decrement the nesting count as the critical section is being
444 * exited. */
445 ulCriticalNesting--;
446
447 /* If the nesting level has reached zero then all interrupt
448 * priorities must be re-enabled. */
449 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
450 {
451 /* Critical nesting has reached zero so all interrupt priorities
452 * should be unmasked. */
453 portCLEAR_INTERRUPT_MASK();
454 }
455 }
456 }
457 /*-----------------------------------------------------------*/
458
FreeRTOS_Tick_Handler(void)459 void FreeRTOS_Tick_Handler( void )
460 {
461 /* Set interrupt mask before altering scheduler structures. The tick
462 * handler runs at the lowest priority, so interrupts cannot already be masked,
463 * so there is no need to save and restore the current mask value. It is
464 * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
465 * updated. */
466 portCPU_IRQ_DISABLE();
467 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
468 __asm volatile ( "dsb \n"
469 "isb \n" ::: "memory" );
470 portCPU_IRQ_ENABLE();
471
472 /* Increment the RTOS tick. */
473 if( xTaskIncrementTick() != pdFALSE )
474 {
475 ulPortYieldRequired = pdTRUE;
476 }
477
478 /* Ensure all interrupt priorities are active again. */
479 portCLEAR_INTERRUPT_MASK();
480 configCLEAR_TICK_INTERRUPT();
481 }
482 /*-----------------------------------------------------------*/
483
484 #if ( configUSE_TASK_FPU_SUPPORT != 2 )
485
vPortTaskUsesFPU(void)486 void vPortTaskUsesFPU( void )
487 {
488 uint32_t ulInitialFPSCR = 0;
489
490 /* A task is registering the fact that it needs an FPU context. Set the
491 * FPU flag (which is saved as part of the task context). */
492 ulPortTaskHasFPUContext = pdTRUE;
493
494 /* Initialise the floating point status register. */
495 __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
496 }
497
498 #endif /* configUSE_TASK_FPU_SUPPORT */
499 /*-----------------------------------------------------------*/
500
vPortClearInterruptMask(uint32_t ulNewMaskValue)501 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
502 {
503 if( ulNewMaskValue == pdFALSE )
504 {
505 portCLEAR_INTERRUPT_MASK();
506 }
507 }
508 /*-----------------------------------------------------------*/
509
ulPortSetInterruptMask(void)510 uint32_t ulPortSetInterruptMask( void )
511 {
512 uint32_t ulReturn;
513
514 /* Interrupt in the CPU must be turned off while the ICCPMR is being
515 * updated. */
516 portCPU_IRQ_DISABLE();
517
518 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
519 {
520 /* Interrupts were already masked. */
521 ulReturn = pdTRUE;
522 }
523 else
524 {
525 ulReturn = pdFALSE;
526 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
527 __asm volatile ( "dsb \n"
528 "isb \n" ::: "memory" );
529 }
530
531 portCPU_IRQ_ENABLE();
532
533 return ulReturn;
534 }
535 /*-----------------------------------------------------------*/
536
537 #if ( configASSERT_DEFINED == 1 )
538
vPortValidateInterruptPriority(void)539 void vPortValidateInterruptPriority( void )
540 {
541 /* The following assertion will fail if a service routine (ISR) for
542 * an interrupt that has been assigned a priority above
543 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
544 * function. ISR safe FreeRTOS API functions must *only* be called
545 * from interrupts that have been assigned a priority at or below
546 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
547 *
548 * Numerically low interrupt priority numbers represent logically high
549 * interrupt priorities, therefore the priority of the interrupt must
550 * be set to a value equal to or numerically *higher* than
551 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
552 *
553 * FreeRTOS maintains separate thread and ISR API functions to ensure
554 * interrupt entry is as fast and simple as possible. */
555 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
556
557 /* Priority grouping: The interrupt controller (GIC) allows the bits
558 * that define each interrupt's priority to be split between bits that
559 * define the interrupt's pre-emption priority bits and bits that define
560 * the interrupt's sub-priority. For simplicity all bits must be defined
561 * to be pre-emption priority bits. The following assertion will fail if
562 * this is not the case (if some bits represent a sub-priority).
563 *
564 * The priority grouping is configured by the GIC's binary point register
565 * (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
566 * possible value (which may be above 0). */
567 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
568 }
569
570 #endif /* configASSERT_DEFINED */
571 /*-----------------------------------------------------------*/
572
vApplicationFPUSafeIRQHandler(uint32_t ulICCIAR)573 void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
574 {
575 ( void ) ulICCIAR;
576 configASSERT( ( volatile void * ) NULL );
577 }
578
