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/Kernel-v10.6.2/.github/workflows/
Dauto-release.yml57 - name: Update source files with version info
66 - name : Update version number in manifest.yml
76 git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml'
89 git commit -m '[AUTO][RELEASE]: Update SBOM'
Dkernel-demos.yml80 sudo apt-get -y update
109 sudo apt-get -y update
133 …git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
151 sudo apt-get -y update
/Kernel-v10.6.2/
DHistory.txt9 - Update the system call entry mechanism to only require one Supervisor
114 + Update eTaskGetState and uxTaskGetSystemState to return eReady for pending ready
116 + Update heap_4 and heap_5 to add padding only if the resulting block is not
129 + Update interrupt priority asserts for Cortex-M ports so that these do not fire
131 + Update ARMv7-M ports to ensure that kernel interrupts run at the lowest priority.
193 - Update the pointer types to portPOINTER_SIZE_TYPE. Contributed by
266 + Update the RL78 IAR port to the latest version of IAR which uses the
284 + Update the uncrustify config file to match the version of the uncrustify
355 + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
390 + Update WolfSSL to 4.5.0 and add the FIPS ready demo.
[all …]
/Kernel-v10.6.2/portable/GCC/STR75x/
Dport.c182 /* Enable TB Update interrupt */ in prvSetupTimerInterrupt()
185 /* Clear TB Update interrupt pending bit */ in prvSetupTimerInterrupt()
/Kernel-v10.6.2/include/
DStackMacros.h31 …#warning The name of this file has changed to stack_macros.h. Please update your code accordingly…
/Kernel-v10.6.2/portable/IAR/STR75x/
Dport.c194 /* Enable TB Update interrupt */ in prvSetupTimerInterrupt()
197 /* Clear TB Update interrupt pending bit */ in prvSetupTimerInterrupt()
/Kernel-v10.6.2/portable/GCC/RISC-V/
Dport.c42 … derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMT…
62 * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
DportASM.S106 /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
124 /* Update the 64-bit mtimer compare match value. */
345 …addi a1, a1, 4 /* Synchronous so update exception return address to the instr…
DportContext.h122 …addi a1, a1, 4 /* Synchronous so update exception return address to the instr…
/Kernel-v10.6.2/portable/IAR/RISC-V/
DportASM.s115 /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
133 /* Update the 64-bit mtimer compare match value. */
360 …addi a1, a1, 4 /* Synchronous so update exception return address to the instr…
Dport.c42 … derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMT…
64 * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
DportContext.h119 …addi a1, a1, 4 /* Synchronous so update exception return address to the instr…
/Kernel-v10.6.2/portable/Paradigm/Tern_EE/small/
Dportasm.h38 * vTaskSwitchContext() to update the TCB being used, then restores the stack
Dport.c160 /* Get the scheduler to update the task states following the tick. */ in prvPreemptiveTick()
/Kernel-v10.6.2/portable/Paradigm/Tern_EE/large_untested/
Dportasm.h35 * vTaskSwitchContext() to update the TCB being used, then restores the stack
/Kernel-v10.6.2/portable/BCC/16BitDOS/common/
Dportasm.h38 * vTaskSwitchContext() to update the TCB being used, then restores the stack
/Kernel-v10.6.2/portable/ThirdParty/XCC/Xtensa/
Dxtensa_vectors.S219 s32i a5, a3, 4 /* update _xt_vpri_mask */
280 /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
286 s32i a2, a3, 4 /* update _xt_vpri_mask */
288 wsr a4, INTENABLE /* update INTENABLE */
727 1: wsr a3, EPC_1 /* update PC */
871 s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */
880 s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */
902 s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */
1783 wsr a2, PS /* update PS.OWB to new window base */
Dportasm.S255 /* Update the timer comparator for the next tick. */
264 wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
287 esync /* ensure comparator update complete */
Dxtensa_context.S287 wsr a4, INTENABLE /* update INTENABLE */
559 s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
/Kernel-v10.6.2/portable/oWatcom/16BitDOS/common/
Dportasm.h35 * vTaskSwitchContext() to update the TCB being used, then restores the stack
/Kernel-v10.6.2/portable/ThirdParty/GCC/Xtensa_ESP32/include/
DFreeRTOSConfig_arch.h59 * Update the code to use esp_clk_cpu_freq function instead.
/Kernel-v10.6.2/portable/ThirdParty/GCC/Xtensa_ESP32/
Dxtensa_vectors.S302 s32i a5, a3, 4 /* update _xt_vpri_mask */
369 /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
375 s32i a2, a3, 4 /* update _xt_vpri_mask */
377 wsr a4, INTENABLE /* update INTENABLE */
899 1: wsr a3, EPC_1 /* update PC */
1084 s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */
1093 s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */
1118 s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */
1920 wsr a2, PS /* update PS.OWB to new window base */
Dportasm.S319 /* Update the timer comparator for the next tick. */
328 wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
351 esync /* ensure comparator update complete */
/Kernel-v10.6.2/portable/MPLAB/PIC32MX/
DISR_Support.h112 /* Update the task stack pointer value if nesting is zero. */
/Kernel-v10.6.2/portable/MPLAB/PIC32MEC14xx/
DISR_Support.h130 /* Update the task stack pointer value if nesting is zero. */

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