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/Kernel-v11.1.0/portable/
DCMakeLists.txt23 # 16-Bit DOS ports for BCC
32 # ARMv7-M port for Texas Instruments Code Composer Studio
37 # ARMv7E-M port for Texas Instruments Code Composer Studio
42 # ARMv7-R port for Texas Instruments Code Composer Studio
47 # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio
52 # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior
64 # ARMv7-A port for GCC
69 # ARMv8-A ports for GCC
78 # ARMv6-M port for GCC
82 # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC
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/Kernel-v11.1.0/
DHistory.txt14 We thank @cperkulator for their contribution.
15 + Add the ability to change task notification index for stream buffers. We
16 thank @glemco for their contribution.
19 We thank @HagaiMoshe for their contribution.
20 + Update all the FreeRTOS APIs to use configSTACK_DEPTH_TYPE for stack type.
21 We thank @feilipu for their contribution.
25 scheduler. We thank @Dazza0 for their contribution.
29 @gemarcano for their inputs.
31 affinity mask for tasks created without an affinity mask. We thank @go2sh
32 for their contribution.
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/Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/
Dreadme_xtensa.txt1 FreeRTOS Port for Xtensa Configurable and Diamond Processors
10 This document describes the Xtensa port for FreeRTOS multitasking RTOS.
11 For an introduction to FreeRTOS itself, please refer to FreeRTOS
24 your application for your Xtensa configuration. The port uses the Xtensa
27 xtensa-linux tools provided you have the correct overlay for your Xtensa
31 This port includes optional reentrancy support for the 'newlib' and
33 thread-safety on a per task basis (for use in tasks only, not interrupt
37 for thread safety. The 'uclibc' library is not reentrant and does not
46 FreeRTOS for Xtensa configurable processors requires the following minimum
55 Minimal support for certain evaluation boards is provided via a board
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Dxtensa_config.h20 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
31 * Configuration-specific information for Xtensa build. This file must be
50 #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
59 * be allocated for saving coprocessor state and/or C library state information
60 * (if thread safety is enabled for the C library). The sizes are in bytes.
62 * Stack sizes for individual tasks should be derived from these minima based on
65 * on the requirement for a task that calls nothing else but can be interrupted.
73 * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
83 * space to be allocated for tasks that use the C library
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Dxtensa_context.h20 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
31 * XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
33 * This header contains definitions and macros for use primarily by Xtensa
61 Macros that help define structures for both C and assembler.
83 INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
85 A stack frame of this structure is allocated for any interrupt or exception.
86 It goes on the current stack. If the RTOS has a system stack for handling
87 interrupts, every thread stack must allow space for just one interrupt stack
94 For Windowed ABI, this stack frame includes the interruptee's base save area,
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Dxtensa_timer.h20 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
31 * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
33 * This header contains definitions and macros for use primarily by Xtensa
61 Select timer to use for periodic tick, and determine its interrupt number
117 Set processor clock frequency, used to determine clock divisor for timer tick.
118 User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
127 real-time performance for most applications under the simulator. A frequency
138 #error "XT_CLOCK_FREQ must be defined for the target platform."
142 Default number of timer "ticks" per second (default 100 for 10ms tick).
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/Kernel-v11.1.0/include/
Dstream_buffer.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
32 * particularly suited for interrupt to task and core to core communication
39 * interrupt that will read from the buffer (the reader). It is safe for the
66 * Type of stream buffer. For internal use only.
73 * Type by which stream buffers are referenced. For example, a call to
96 * xStreamBufferCreateStatic() for a version that uses statically allocated
100 * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
101 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
108 * buffer before a task that is blocked on the stream buffer to wait for data is
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Dtask.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
76 * configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the
84 * Type by which tasks are referenced. For example, a call to xTaskCreate
174 …tackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the …
176 UBaseType_t uxCoreAffinityMask; /* The core affinity mask for the task */
180 /* Possible return values for eTaskConfirmSleepModeStatus(). */
187 …eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode t…
208 * Macro for forcing a context switch.
312 * See xTaskCreateStatic() for a version that does not use any dynamic memory
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Devent_groups.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
67 * meaning. For example, an application may create an event group to convey
69 * message has been received and is ready for processing", bit 1 might mean "The
70 * application has queued a message that is ready for sending onto the CAN
73 * are active, and optionally enter the Blocked state to wait for a specified
83 * variable for the same purpose. This is particularly important with respect
95 * Type by which event groups are referenced. For example, a call to
133 * Although event groups are not related to ticks, for internal implementation
134 * reasons the number of bits available for use in an event group is dependent
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Dmessage_buffer.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
35 * implementation is light weight, making them particularly suited for interrupt
42 * interrupt that will read from the buffer (the reader). It is safe for the
80 * Type by which message buffers are referenced. For example, a call to
98 * xMessageBufferCreateStatic() for a version that uses statically allocated
102 * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
103 * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
126 * because there is insufficient heap memory available for FreeRTOS to allocate
177 * xMessageBufferCreate() for a version that uses dynamically allocated memory.
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Dcroutine.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
78 * documentation for more information.
85 * of the WEB documentation for further information.
96 * // This may not be necessary for const variables.
103 * for( ;; )
105 * // This co-routine just delays for a fixed period, then toggles
127 * for( uxIndex = 0; uxIndex < 2; uxIndex++ )
172 * for( ;; )
202 * for( ;; )
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Dsemphr.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
67 * This type of semaphore can be used for pure synchronisation between tasks or
70 * another continuously 'takes' the semaphore. For this reason this type of
71 * semaphore does not use a priority inheritance mechanism. For an alternative
136 * This type of semaphore can be used for pure synchronisation between tasks or
139 * another continuously 'takes' the semaphore. For this reason this type of
140 * semaphore does not use a priority inheritance mechanism. For an alternative
192 * This type of semaphore can be used for pure synchronisation between tasks or
195 * another continuously 'takes' the semaphore. For this reason this type of
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Dqueue.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
46 * Type by which queues are referenced. For example, a call to xQueueCreate()
54 * Type by which queue sets are referenced. For example, a call to
67 /* For internal use only. */
72 /* For internal use only. These definitions *must* match those in queue.c. */
108 * that will be copied for each posted item. Each item on the queue must be
182 * that will be copied for each posted item. Each item on the queue must be
250 * @param xQueue The queue for which to retrieve the buffers.
279 * routine. See xQueueSendFromISR () for an alternative which may be used
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/Kernel-v11.1.0/portable/GCC/MicroBlazeV8/
Dportmacro.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
45 * The settings in this file configure FreeRTOS correctly for the
232 * Installs pxHandler as the interrupt handler for the peripheral specified by
239 * is itself part of the BSP project. For example, in the official demo
240 * application for this port, xparameters.h defines the following IDs for the
243 * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
244 * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
245 * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
246 * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
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/Kernel-v11.1.0/portable/GCC/MicroBlazeV9/
Dportmacro.h19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
45 * The settings in this file configure FreeRTOS correctly for the
247 * Installs pxHandler as the interrupt handler for the peripheral specified by
254 * is itself part of the BSP project. For example, in the official demo
255 * application for this port, xparameters.h defines the following IDs for the
258 * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral.
259 * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral.
260 * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral.
261 * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
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Dport.c19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
30 * Implementation of functions defined in portable.h for the MicroBlaze port.
59 * given to the FSR register when the initial context is set up for a task being
63 * Global counter used for calculation of run time statistics of tasks.
89 /* This port uses a separate stack for interrupts. This prevents the stack of
99 * an unusual mechanism, but is used for this port because a single interrupt can
135 * This is essential for the Microblaze port and these lines must in pxPortInitialiseStack()
160 * the running state for the first time. */ in pxPortInitialiseStack()
165 /* Ensure exceptions are enabled for the task. */ in pxPortInitialiseStack()
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/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/include/
Dxtensa_config.h25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
34 * Configuration-specific information for Xtensa build. This file must be
54 #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
63 * be allocated for saving coprocessor state and/or C library state information
64 * (if thread safety is enabled for the C library). The sizes are in bytes.
66 * Stack sizes for individual tasks should be derived from these minima based on
69 * on the requirement for a task that calls nothing else but can be interrupted.
77 * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
87 * space to be allocated for tasks that use the C library
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Dxtensa_timer.h25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
26 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
34 * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
36 * This header contains definitions and macros for use primarily by Xtensa
65 * Select timer to use for periodic tick, and determine its interrupt number
121 * Set processor clock frequency, used to determine clock divisor for timer tick.
122 * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
131 * real-time performance for most applications under the simulator. A frequency
142 #error "XT_CLOCK_FREQ must be defined for the target platform."
146 * Default number of timer "ticks" per second (default 100 for 10ms tick).
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/Kernel-v11.1.0/portable/MPLAB/PIC18F/
Dport.c19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
40 incorrect address for compatibility mode of 0x18.
46 for the enhancement.
66 * Implementation of functions defined in portable.h for the PIC port.
69 /* Hardware setup for tick. */
72 /* Initial interrupt enable state for newly created tasks. This value is
73 copied into INTCON when a task switches in for the first time. */
76 /* Just the bit within INTCON for the global interrupt flag. */
79 /* Constant used for context switch macro when we require the interrupt
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/Kernel-v11.1.0/portable/ThirdParty/GCC/ATmega/
Dreadme.md3 __Port for generalised Microchip ATmega architecture__
7 This port provides a basis for supporting all modern ATmega devices using either the Enhanced Watch…
14 …for 16-bit Timers available on many relevant devices. The availability of these 16-bit Timers is s…
16 …for the 3 byte program counter devices __ATmega2560__ and __ATmega2561__. Specific to these two de…
22 …for generating phase correct PWM by up/down counting), and Pins attached to Interrupts. The 8-bit …
36 … These are the __ATmega2560__ and __ATmega2561__. This PR provides support for these two devices i…
41 For devices which can support __XRAM__ and have the __RAMPZ__ register, this register is also prese…
49 …for the Scheduler), and enable interrupts to be nested. Using this method, I've been able to succe…
55 …ir own heap using one of the pre-allocated heap management algorithms, but for those that choose t…
57 The avr-libc library assumes that the stack will always be above the heap, and does a check for thi…
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/Kernel-v11.1.0/portable/IAR/RISC-V/
DportASM.s19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
44 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
49 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
54 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
69 …ed. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIM…
123 …Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for …
137 add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
147 * for the function is as per the other ports:
154 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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/Kernel-v11.1.0/portable/GCC/RISC-V/
DportASM.S19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
44 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
49 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
54 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
69 …ed. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIM…
114 …Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for …
128 add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
138 * for the function is as per the other ports:
145 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
Dxtensa_vectors.S24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
34 XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
36 Xtensa low level exception and interrupt vectors and handlers for an RTOS.
43 Users can install application-specific interrupt handlers for low and
55 '-DXT_INTEXC_HOOKS' (useful for automated testing).
58 !! application specific interrupts. Search USER_EDIT for helpful comments !!
63 provided for each exception type. Note that some exceptions are handled
80 defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
82 For example, this file provides interrupt vector templates for all types and
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/Kernel-v11.1.0/portable/IAR/ARM_CM7/r0p1/
Dport.c19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
30 * Implementation of functions defined in portable.h for the ARM CM7 port.
104 /* For strict compliance with the Cortex-M spec the task start address should
174 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
195 * See header file for description.
204 /* Offset added to account for the way the MCU uses the stack on entry/exit in pxPortInitialiseStack()
240 for( ; ; ) in prvTaskExitError()
247 * See header file for description.
254 * xPortPendSVHandler for SVCall and PendSV interrupts respectively. in xPortStartScheduler()
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/Kernel-v11.1.0/portable/IAR/ARM_CM3/
Dport.c19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
30 * Implementation of functions defined in portable.h for the ARM CM3 port.
95 /* For strict compliance with the Cortex-M spec the task start address should
160 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
181 * See header file for description.
189 … /* Offset added to account for the way the MCU use… in pxPortInitialiseStack()
214 for( ; ; ) in prvTaskExitError()
221 * See header file for description.
228 * xPortPendSVHandler for SVCall and PendSV interrupts respectively. in xPortStartScheduler()
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