| /Kernel-v11.1.0/portable/Renesas/SH2A_FPU/ |
| D | portasm.src | 101 fmov.s fr0, @-r4
102 fmov.s fr1, @-r4
103 fmov.s fr2, @-r4
104 fmov.s fr3, @-r4
105 fmov.s fr4, @-r4
106 fmov.s fr5, @-r4
107 fmov.s fr6, @-r4
108 fmov.s fr7, @-r4
109 fmov.s fr8, @-r4
110 fmov.s fr9, @-r4
[all …]
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| /Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/ |
| D | Makefile | 22 SRCROOT = $(subst /,$(S),$(CURDIR))
23 TSTROOT = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
24 BLDROOT = $(TSTROOT)$(S)build
25 BLDDIR = $(BLDROOT)$(S)$(XT_CORE)
27 FR_SRCDIR = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)
28 FR_SRCDIR2 = $(FR_SRCDIR)$(S)portable$(S)MemMang
32 vpath %.S $(XT_SRCDIR)
38 XT_S_FILES = $(notdir $(wildcard $(XT_SRCDIR)/*.S))
43 LIB_S_O = $(patsubst %.S,%.o,$(XT_S_FILES))
48 OSLIB = $(BLDDIR)$(S)libfreertos.a
[all …]
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| D | xtensa_vectors.S | 37 after user's specific interrupt handlers. These macros are defined in
212 addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */
337 Initialized with all 0s, meaning no handler is installed at each level.
367 user's interrupt handler code (which may be coded in C) and finally
564 rsr a0, PS /* save interruptee's PS */
566 rsr a0, EPC_1 /* save interruptee's PC */
568 rsr a0, EXCSAVE_1 /* save interruptee's a0 */
642 l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
644 l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
646 l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
[all …]
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| D | xtensa_context.h | 91 by user TIE or the use of the MAC16 option in the user's Xtensa config.
92 The frame size is minimized by omitting regs not applicable to user's config.
94 For Windowed ABI, this stack frame includes the interruptee's base save area,
169 This is the frame size. Add space for 4 registers (interruptee's base save
182 It goes on the current thread's stack.
185 by the callee according to the compiler's ABI conventions, some space to save
186 the return address for returning to the caller, and the caller's PS register.
188 For Windowed ABI, this stack frame includes the caller's base save area.
236 Ownership represents which thread's state is currently in the co-processor.
254 The contents of a non-running thread's CPENABLE register.
[all …]
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| D | portasm.S | 83 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
107 Save interrupted task's SP in TCB only if not nesting.
136 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
138 * switching, restore the (possibly) new task's context, and return to the
139 * exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
199 In either case there's no need to load the SP.
207 this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
219 * Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
350 * If restoring a task that was preempted, restores all state including the task's CPENABLE.
409 /* Restore CPENABLE from task's co-processor save area. */
[all …]
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| /Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/ |
| D | xtensa_vectors.S | 40 after user's specific interrupt handlers. These macros are defined in
129 To create the pseudo base-save area, we need to store a copy of the pre-exception's
130 base save area (a0 to a4) below the exception dispatcher's SP. EXCSAVE_x will
131 be used to store a copy of the SP that points to the interrupted code's exception
132 frame just in case the exception dispatcher's SP does not point to the exception
240 pre-exception's base save area below the current SP.
252 Also need to change current frame's return address to point to pre-exception's
295 addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */
411 rsr a0, PS /* save interruptee's PS */
413 rsr a0, EPC_1 /* save interruptee's PC */
[all …]
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| D | portmux_impl.inc.h | 62 … "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, ow…
105 …ets_printf( "Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLock…
129 …ets_printf( "Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux-…
175 …ets_printf( "Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLo…
179 … assert( coreID == mux->owner ); /* This is a mutex we didn't lock, or it's corrupt */
191 …ets_printf( "Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, la…
|
| D | portasm.S | 97 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
121 Save interrupted task's SP in TCB only if not nesting.
177 * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
179 * switching, restore the (possibly) new task's context, and return to the
180 * exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
256 In either case there's no need to load the SP.
264 this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
276 * Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
424 * If restoring a task that was preempted, restores all state including the task's CPENABLE.
491 /* Restore CPENABLE from task's co-processor save area. */
[all …]
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| /Kernel-v11.1.0/portable/ |
| D | CMakeLists.txt | 55 CodeWarrior/ColdFire_V1/portasm.S>
59 CodeWarrior/ColdFire_V2/portasm.S>
67 GCC/ARM_CA9/portASM.S>
72 GCC/ARM_AARCH64/portASM.S>
76 GCC/ARM_AARCH64_SRE/portASM.S>
208 GCC/ARM_CR5/portASM.S>
212 GCC/ARM_CRx_MPU/portASM.S
213 GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S>
217 GCC/ARM_CRx_No_GIC/portASM.S>
256 GCC/AVR32_UC3/exception.S
[all …]
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| /Kernel-v11.1.0/portable/IAR/RISC-V/chip_specific_extensions/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
20 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/IAR/RISC-V/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
20 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
20 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
17 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
18 * compiler's!) include path. For example, if the chip in use includes a core
20 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/ |
| D | portmacro_asm.h | 109 * Further information about MPU can be found in Arm's documentation
168 /* MPU memory types. This information is encoded in the TEX, S, C and B bits
170 #define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x00UL ) /* TEX=000, S=NA, C=0, B=0. */
171 #define portMPU_REGION_DEVICE_SHAREABLE ( 0x01UL ) /* TEX=000, S=NA, C=0, B=1. */
172 #define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x02UL ) /* TEX=000, S=0, C=1, B=0. */
173 #define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x06UL ) /* TEX=000, S=1, C=1, B=0. */
174 #define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x03UL ) /* TEX=000, S=0, C=1, B=1. */
175 #define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x07UL ) /* TEX=000, S=1, C=1, B=1. */
176 #define portMPU_REGION_NORMAL_OINC_NONSHARED ( 0x08UL ) /* TEX=001, S=0, C=0, B=0. */
177 #define portMPU_REGION_NORMAL_OINC_SHARED ( 0x0CUL ) /* TEX=001, S=1, C=0, B=0. */
[all …]
|
| /Kernel-v11.1.0/portable/ARMv8M/ |
| D | copy_files.py | 99 'ARM_CM35P' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
100 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
102 … 'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
103 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
105 'ARM_CM55' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
106 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
108 … 'ARM_CM55_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
109 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'),
111 'ARM_CM85' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
112 … os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'),
[all …]
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
34 * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
46 * compiler's!) include path. For example, if the chip in use includes a core
48 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
34 * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
46 * compiler's!) include path. For example, if the chip in use includes a core
48 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
46 * compiler's!) include path. For example, if the chip in use includes a core
48 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
46 * compiler's!) include path. For example, if the chip in use includes a core
48 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/portable/ThirdParty/xClang/XCOREAI/ |
| D | portasm.S | 24 {set sp, r4 /* Restore the task's SP to save the rest of its context. */
34 /* start saving the thread's context */
58 /* Save the thread's context onto the thread's stack. */
89 {set sp, r4 /* Restore the task's SP now. */
100 /* Save the rest of the current task's context. */
127 ldw r1, r5[r0] /* Get this core's current TCB pointer into r1. */
128 stw r4, r1[0x0] /* Save the current task's SP to the first */
135 bla r11 /* Finally call vTaskSwitchContext(core_id) now that the task's */
144 ldw r0, r5[r6] /* get this core's current TCB pointer into r0 */
148 /* Restore the current task's context */
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/ |
| D | freertos_risc_v_chip_specific_extensions.h | 30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
45 * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
46 * compiler's!) include path. For example, if the chip in use includes a core
48 * extensions then add the path below to the assembler's include path:
|
| /Kernel-v11.1.0/include/ |
| D | task.h | 116 eSetBits, /* Set bits in the task's notification value. */
117 eIncrement, /* Increment the task's notification value. */
118 …eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the pre…
119 …eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read…
163 …const char * pcTaskName; /* A pointer to the task's name. This value will be…
167 … /* The priority to which the task will return if the task's current priority has…
169 …StackType_t * pxStackBase; /* Points to the lowest address of the task's stack …
171 …StackType_t * pxTopOfStack; /* Points to the top address of the task's stack area. */
172 …StackType_t * pxEndOfStack; /* Points to the end address of the task's stack area. */
303 * memory. The first block is used to hold the task's data structures. The
[all …]
|
| /Kernel-v11.1.0/portable/WizC/PIC18/ |
| D | portmacro.h | 175 * Macro's that pushes all the registers that make up the context of a task onto
199 * The total overheadstorage has to be saved in it's entirety as part of
200 * a task context. These macro's store/restore from data address 0x0000 to
213 ; Push the relevant SFR's onto the task's stack \
246 ; current task by copying it to the task's software- \
250 ; is modified in the save-loop by executing pop's. \
338 ; Restore the compiler's working storage area to page 0 \
349 ; Restore the sfr's forming the tasks context. \
|
| /Kernel-v11.1.0/portable/IAR/ARM_CM4F_MPU/ |
| D | portmacro.h | 98 /* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
110 * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
119 * For Normal memory regions, the S bit indicates whether the region is
120 * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
122 * See the following two tables for setting TEX, S, C and B bits for
132 … | Outer and inner write-through; no write allocate | S bit …
134 … | Outer and inner write-back; no write allocate | S bit …
136 … | Outer and inner Non-cacheable | S bit …
142 … | Outer and inner write-back; write and read allocate | S bit …
171 /* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
[all …]
|
| /Kernel-v11.1.0/portable/GCC/ARM_CM0/ |
| D | portmacro.h | 128 /* Shareable (S), Cacheable (C) and Bufferable (B) bits for flash region. */
133 /* Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM region. */
176 /* MPU memory types. This information is encoded in the S ( Shareable), C
179 #define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x0UL << 16UL ) /* S=NA, C=0, B=0. */
180 #define portMPU_REGION_DEVICE_SHAREABLE ( 0x1UL << 16UL ) /* S=NA, C=0, B=1. */
181 #define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x2UL << 16UL ) /* S=0, C=1, B=0. */
182 #define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x6UL << 16UL ) /* S=1, C=1, B=0. */
183 #define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x3UL << 16UL ) /* S=0, C=1, B=1.*/
184 #define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x7UL << 16UL ) /* S=1, C=1, B=1.*/
|
