Searched +full:- +full:v (Results 1 – 25 of 28) sorted by relevance
12
| /Kernel-v11.1.0/portable/IAR/RISC-V/chip_specific_extensions/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
21 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
| /Kernel-v11.1.0/portable/IAR/RISC-V/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
21 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
| D | portASM.s | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
34 * + The code that is common to all RISC-V chips is implemented in
35 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
36 * portASM.S file because the same file is used no matter which RISC-V chip is
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
42 * RISC-V chip that both includes a standard CLINT and does not add to the
43 * base set of RISC-V registers. There are additional
[all …]
|
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the RISC-V port.
31 *----------------------------------------------------------*/
42 …directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
46 …-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set con…
50 …-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise s…
53 /* Let the user override the pre-loading of the initial LR with the address of
95 /*-----------------------------------------------------------*/
100 …( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
[all …]
|
| D | portmacro.h | 5 * SPDX-License-Identifier: MIT
35 /* *INDENT-OFF* */
39 /* *INDENT-ON* */
41 /*-----------------------------------------------------------
48 *-----------------------------------------------------------
79 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
82 /*-----------------------------------------------------------*/
85 #define portSTACK_GROWTH ( -1 )
88 …#define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment req…
92 /*-----------------------------------------------------------*/
[all …]
|
| D | Documentation.url | 1 [{000214A0-0000-0000-C000-000000000046}]
5 URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
| D | portContext.h | 5 * SPDX-License-Identifier: MIT
48 * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
66 /*-----------------------------------------------------------*/
69 addi sp, sp, -portCONTEXT_SIZE
107 …tos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
113 /*-----------------------------------------------------------*/
123 /*-----------------------------------------------------------*/
132 /*-----------------------------------------------------------*/
142 …_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
187 /*-----------------------------------------------------------*/
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
21 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/ |
| D | readme.txt | 2 * The FreeRTOS kernel's RISC-V port is split between the the code that is
3 * common across all currently supported RISC-V chips (implementations of the
4 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
6 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
7 * is common to all currently supported RISC-V chips. There is only one
8 * portASM.S file because the same file is built for all RISC-V target chips.
11 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
13 * as there are multiple RISC-V chip implementations.
21 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
| D | portASM.S | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
34 * + The code that is common to all RISC-V chips is implemented in
35 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
36 * portASM.S file because the same file is used no matter which RISC-V chip is
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
42 * RISC-V chip that both includes a standard CLINT and does not add to the
43 * base set of RISC-V registers. There are additional
[all …]
|
| D | port.c | 5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
30 * Implementation of functions defined in portable.h for the RISC-V port.
31 *----------------------------------------------------------*/
42 … directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
46 …-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set con…
50 …-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise s…
53 /* Let the user override the pre-loading of the initial RA. */
87 /*-----------------------------------------------------------*/
92 …( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
[all …]
|
| D | Documentation.url | 1 [{000214A0-0000-0000-C000-000000000046}]
5 URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
| D | portContext.h | 5 * SPDX-License-Identifier: MIT
48 * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
61 /*-----------------------------------------------------------*/
67 /*-----------------------------------------------------------*/
70 addi sp, sp, -portCONTEXT_SIZE
110 …tos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
116 /*-----------------------------------------------------------*/
126 /*-----------------------------------------------------------*/
135 /*-----------------------------------------------------------*/
145 …_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
[all …]
|
| D | portmacro.h | 5 * SPDX-License-Identifier: MIT
33 /* *INDENT-OFF* */
37 /* *INDENT-ON* */
39 /*-----------------------------------------------------------
46 *-----------------------------------------------------------
77 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
80 /*-----------------------------------------------------------*/
83 #define portSTACK_GROWTH ( -1 )
86 …#define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment require…
90 /*-----------------------------------------------------------*/
[all …]
|
| /Kernel-v11.1.0/portable/WizC/PIC18/ |
| D | Install.bat | 16 echo YES, I found a fedC-installation!
19 echo I could not find a fedC-installation.
27 echo YES, I found a wizC-installation!
30 echo I could not find a wizC-installation.
36 echo I could not find a FED C-compiler installation on your system.
38 echo Perhaps I got confused because you installed fedC or wizC in a non-default directory.
39 echo If this is the case, please change the path at the top of this install-script.
65 echo Press 'ctrl-c' to stop me
74 attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul
75 attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul
[all …]
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
49 * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
49 * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions
|
| /Kernel-v11.1.0/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
49 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
[all …]
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
49 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
[all …]
|
| /Kernel-v11.1.0/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/ |
| D | freertos_risc_v_chip_specific_extensions.h | 5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
34 * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
35 * is common to all currently supported RISC-V chips. There is only one
36 * portASM.S file because the same file is built for all RISC-V target chips.
39 * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
41 * as there are multiple RISC-V chip implementations.
49 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
[all …]
|
| /Kernel-v11.1.0/portable/ThirdParty/GCC/RISC-V/ |
| D | README-for-info-on-official-MIT-license-port.txt | 1 The official and MIT licensed FreeRTOS ports for RISC-V are located in the following directories:
2 \FreeRTOS\Source\portable\GCC\RISC-V
3 \FreeRTOS\Source\portable\IAR\RISC-V
5 Also so https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
| /Kernel-v11.1.0/portable/ |
| D | CMakeLists.txt | 2 include( GCC/RISC-V/chip_extensions.cmake )
6 include( IAR/RISC-V/chip_extensions.cmake )
9 # FreeRTOS internal cmake file. Do not use it in user top-level project
16 # FreeRTOS internal cmake file. Do not use it in user top-level project
23 # 16-Bit DOS ports for BCC
32 # ARMv7-M port for Texas Instruments Code Composer Studio
37 # ARMv7E-M port for Texas Instruments Code Composer Studio
42 # ARMv7-R port for Texas Instruments Code Composer Studio
44 CCS/ARM_Cortex-R4/port.c
45 CCS/ARM_Cortex-R4/portASM.asm>
[all …]
|
| /Kernel-v11.1.0/.github/scripts/ |
| D | manifest_updater.py | 14 updated_lines.append(f'version: "v{new_version_number}"\n')
23 parser.add_argument('-v', '--version', required=True, help='New version number.')
|
| /Kernel-v11.1.0/ |
| D | CMakeLists.txt | 9 # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined fo…
31 …message(WARNING " Using deprecated 'FREERTOS_CONFIG_FILE_DIRECTORY' - please update your project C…
44 …message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):…
47 " -DFREERTOS_PORT=GCC_ARM_CM4F\n"
50 " A_CUSTOM_PORT - Compiler: User Defined Target: User Defined\n"
51 " BCC_16BIT_DOS_FLSH186 - Compiler: BCC Target: 16 bit DOS Flsh186\n"
52 " BCC_16BIT_DOS_PC - Compiler: BCC Target: 16 bit DOS PC\n"
53 " CCS_ARM_CM3 - Compiler: CCS Target: ARM Cortex-M3\n"
54 … " CCS_ARM_CM4F - Compiler: CCS Target: ARM Cortex-M4 with FPU\n"
55 " CCS_ARM_CR4 - Compiler: CCS Target: ARM Cortex-R4\n"
[all …]
|
| /Kernel-v11.1.0/.github/workflows/ |
| D | auto-release.yml | 1 name: Kernel-Auto-Release
15 description: "Version String for task.h on main branch (leave empty to leave as-is)."
20 release-packager:
22 runs-on: ubuntu-latest
25 - name: Tool Setup
26 uses: actions/setup-python@v2
33 - name: Checkout FreeRTOS Release Tools
40 - name: Checkout FreeRTOS Kernel
44 fetch-depth: 0
46 - name: Configure git identity
[all …]
|
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